Update test/npu-xrt/adjacent_memtile_access/two_memtiles/aie2.py

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Xilinx · Nov 19, 2024 · 7b79747 · 7b79747
1 parent 3cd6c22
commit 7b79747
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/test/npu-xrt/adjacent_memtile_access/two_memtiles/aie2.py b/test/npu-xrt/adjacent_memtile_access/two_memtiles/aie2.py
@@ -168,8 +168,7 @@ def sequence(A, B, C):
             npu_dma_memcpy_nd(metadata="in1", bd_id=1, mem=A, sizes=[1, 1, 1, N])
             npu_dma_memcpy_nd(metadata="out", bd_id=0, mem=C, sizes=[1, 1, 1, N])
             npu_dma_wait("out")
-            #npu_sync(column=0, row=0, direction=0, channel=0)
-
+            # npu_sync(column=0, row=0, direction=0, channel=0)
 
 
 with mlir_mod_ctx() as ctx: