move dialect tests to aie-opt (#1459)

Xilinx · May 7, 2024 · 7977782 · 7977782
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commit 7977782
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diff --git a/test/dialect/AIE/badbuffer-ve2802.mlir b/test/dialect/AIE/badbuffer-ve2802.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // Row 2 is a memtile, not a coretile.
 // CHECK: error{{.*}}'aie.buffer' op in Column 1 and Row 2 is accessed from an unreachable tile in Column 1 and Row 3
 

diff --git a/test/dialect/AIE/badbuffer.mlir b/test/dialect/AIE/badbuffer.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.buffer' op in Column 1 and Row 1 is accessed from an unreachable tile in Column 4 and Row 4
 
 module @test {

diff --git a/test/dialect/AIE/badconnect.mlir b/test/dialect/AIE/badconnect.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}} 'aie.connect' op source index cannot be less than zero
 
 module {

diff --git a/test/dialect/AIE/badcore.mlir b/test/dialect/AIE/badcore.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.core' op failed to verify that op exists in a core tile
 
 module @test {

diff --git a/test/dialect/AIE/badcore2.mlir b/test/dialect/AIE/badcore2.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.core' op failed to verify that op exists in a core tile
 
 module @test {

diff --git a/test/dialect/AIE/badlock-vc1902.mlir b/test/dialect/AIE/badlock-vc1902.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.lock' op lock assigned invalid id (maximum is 15)
 module @test {
   %t1 = aie.tile(1, 1)

diff --git a/test/dialect/AIE/badlock-ve2802.mlir b/test/dialect/AIE/badlock-ve2802.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.lock' op lock assigned invalid id (maximum is 63)
 module @test {
   aie.device(xcve2802) {

diff --git a/test/dialect/AIE/badlockdma.mlir b/test/dialect/AIE/badlockdma.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.lock' op in Column 4 and Row 4 is accessed from an unreachable tile in Column 1 and Row 1
 module @test {
   %t1 = aie.tile(1, 1)

diff --git a/test/dialect/AIE/badlockfunc.mlir b/test/dialect/AIE/badlockfunc.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.lock' op is accessed outside of a tile
 module @test {
   %t1 = aie.tile(1, 1)

diff --git a/test/dialect/AIE/badmemtiledma_neighboraccess.mlir b/test/dialect/AIE/badmemtiledma_neighboraccess.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.buffer' op in Column 3 and Row 1 is accessed from an unreachable tile in Column 1 and Row 1
 
 // memtiles can only access neighboring memtiles

diff --git a/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir b/test/dialect/AIE/badswitchbox_memtile_nofifo-ve2802.mlir
@@ -9,7 +9,7 @@
 //===----------------------------------------------------------------------===//
 
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.connect' op source bundle FIFO not supported
 
 module {

diff --git a/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir b/test/dialect/AIE/badswitchbox_shimtile_nodma-ve2802.mlir
@@ -9,7 +9,7 @@
 //===----------------------------------------------------------------------===//
 
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.connect' op source bundle DMA not supported
 
 module {

diff --git a/test/dialect/AIE/badtile-ve2802.mlir b/test/dialect/AIE/badtile-ve2802.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.tile' op column index (50) must be less than the number of columns in the device (38)
 
 module @test {

diff --git a/test/dialect/AIE/badtile.mlir b/test/dialect/AIE/badtile.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.tile' op attribute 'col' failed to satisfy constraint: 32-bit signless integer attribute whose minimum value is 0
 
 module @test {

diff --git a/test/dialect/AIE/badtile2.mlir b/test/dialect/AIE/badtile2.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.tile' op column index (50) must be less than the number of columns in the device (50)
 
 module @test {

diff --git a/test/dialect/AIE/badtiledma.mlir b/test/dialect/AIE/badtiledma.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.use_lock' op used in a DMA block that have multiple locks.
 
 module @test {

diff --git a/test/dialect/AIE/badtiledma2.mlir b/test/dialect/AIE/badtiledma2.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.dma_bd' op Core tile DMAs can only access a buffer in the same tile.
 
 module @test {

diff --git a/test/dialect/AIE/badtiledma3.mlir b/test/dialect/AIE/badtiledma3.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: not %PYTHON aiecc.py --basic-alloc-scheme %s 2>&1 | FileCheck %s
+// RUN: not aie-opt %s 2>&1 | FileCheck %s
 // CHECK: error{{.*}}'aie.use_lock' op can only access a lock in the same tile
 
 module @test {