Remove CallableOpInterface from MemOp and MemTileOp (#1915)

Xilinx · Nov 12, 2024 · 4604956 · 4604956
1 parent cdf5681
commit 4604956
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Showing 3 changed files with 21 additions and 44 deletions.
diff --git a/include/aie/Dialect/AIE/IR/AIEOps.td b/include/aie/Dialect/AIE/IR/AIEOps.td
@@ -1046,10 +1046,8 @@ def AIE_DMAOp: AIE_Op<"dma", [
   }];
 }
 
-// MemOps are not actually Callable, but we want to inline code into them, so we have to
-// implement CallableOpInterface
 def AIE_MemOp: AIE_Op<"mem", [
-    TileElement, FlowEndPoint, CallableOpInterface,
+    TileElement, FlowEndPoint,
     IsCoreTile, HasValidBDs, HasValidDMAChannels,
     DeclareOpInterfaceMethods<InferTypeOpInterface>
   ]>, Results<(outs Index)> {
@@ -1084,19 +1082,12 @@ def AIE_MemOp: AIE_Op<"mem", [
     int colIndex();
     int rowIndex();
     TileOp getTileOp();
-    int maxSizeInBytes() { return 32768; }
-    // CallableOpInterface
-    mlir::Region *getCallableRegion();
-    llvm::ArrayRef<mlir::Type> getArgumentTypes() { return getOperand().getType(); }
-    llvm::ArrayRef<mlir::Type> getResultTypes() { return getType(); }
     using ::xilinx::AIE::TileElement::Trait<MemOp>::getAsmResultNames;
   }];
 }
 
-// This op is not actually Callable, but we want to inline code into them, so we have to
-// implement CallableOpInterface
 def AIE_MemTileDMAOp: AIE_Op<"memtile_dma", [
-    TileElement, FlowEndPoint, CallableOpInterface,
+    TileElement, FlowEndPoint,
     IsMemTile, HasValidBDs, HasValidDMAChannels,
     DeclareOpInterfaceMethods<InferTypeOpInterface>
   ]>, Results<(outs Index)> {
@@ -1135,10 +1126,6 @@ def AIE_MemTileDMAOp: AIE_Op<"memtile_dma", [
     int colIndex();
     int rowIndex();
     TileOp getTileOp();
-    // CallableOpInterface
-    mlir::Region *getCallableRegion();
-    llvm::ArrayRef<mlir::Type> getArgumentTypes() { return getOperand().getType(); }
-    llvm::ArrayRef<mlir::Type> getResultTypes() { return getType(); }
     using ::xilinx::AIE::TileElement::Trait<MemTileDMAOp>::getAsmResultNames;
   }];
 }

diff --git a/lib/Dialect/AIE/IR/AIEDialect.cpp b/lib/Dialect/AIE/IR/AIEDialect.cpp
@@ -1500,11 +1500,6 @@ int MemOp::colIndex() { return getTileOp().colIndex(); }
 
 int MemOp::rowIndex() { return getTileOp().rowIndex(); }
 
-/// Returns the region on the current operation that is callable. This may
-/// return nullptr in the case of an external callable object, e.g. an external
-/// function.
-Region *MemOp::getCallableRegion() { return &getBody(); }
-
 //===----------------------------------------------------------------------===//
 // MemTileDMAOp
 //===----------------------------------------------------------------------===//
@@ -1939,11 +1934,6 @@ int MemTileDMAOp::colIndex() { return getTileOp().colIndex(); }
 
 int MemTileDMAOp::rowIndex() { return getTileOp().rowIndex(); }
 
-/// Returns the region on the current operation that is callable. This may
-/// return nullptr in the case of an external callable object, e.g. an
-/// external function.
-Region *MemTileDMAOp::getCallableRegion() { return &getBody(); }
-
 //===----------------------------------------------------------------------===//
 // SwitchboxOp
 //===----------------------------------------------------------------------===//

diff --git a/lib/Dialect/AIEX/IR/AIEXDialect.cpp b/lib/Dialect/AIEX/IR/AIEXDialect.cpp
@@ -31,7 +31,12 @@ void AIEXDialect::initialize() {
       >();
 }
 
-uint64_t getBufferDescriptorAddressRegisterAddress(
+} // namespace xilinx::AIEX
+
+#define GET_OP_CLASSES
+#include "aie/Dialect/AIEX/IR/AIEX.cpp.inc"
+
+uint64_t AIEX::getBufferDescriptorAddressRegisterAddress(
     const AIE::AIETargetModel &tm, unsigned bd_id, unsigned col, unsigned row) {
   assert(bd_id < tm.getNumBDs(col, row));
   return ((col & 0xff) << tm.getColumnShift()) |
@@ -71,12 +76,12 @@ uint64_t getBufferDescriptorAddressRegisterAddress(
   Note: strides are expressed offset by one from user input strides, because the
   hardware does not support a 0 stride (repeat).
   */
-void getHardwareStridesWraps(const AIE::AIETargetModel &targetModel,
-                             mlir::MemRefType referencedBufType,
-                             llvm::SmallVector<int64_t, 4> inputSizes,
-                             llvm::SmallVector<int64_t, 4> inputStrides,
-                             llvm::SmallVector<int64_t, 4> &sizes,
-                             llvm::SmallVector<int64_t, 4> &strides) {
+void AIEX::getHardwareStridesWraps(const AIE::AIETargetModel &targetModel,
+                                   mlir::MemRefType referencedBufType,
+                                   llvm::SmallVector<int64_t, 4> inputSizes,
+                                   llvm::SmallVector<int64_t, 4> inputStrides,
+                                   llvm::SmallVector<int64_t, 4> &sizes,
+                                   llvm::SmallVector<int64_t, 4> &strides) {
   assert(inputSizes.size() == inputStrides.size());
   assert(sizes.size() == 4);
   assert(strides.size() == 4);
@@ -140,13 +145,13 @@ void getHardwareStridesWraps(const AIE::AIETargetModel &targetModel,
 }
 
 mlir::LogicalResult
-verifyStridesWraps(mlir::Operation *forOp, mlir::MemRefType referencedBufType,
-                   int tileCol, int tileRow,
-                   llvm::SmallVector<int64_t, 4> inputSizes,
-                   llvm::SmallVector<int64_t, 4> inputStrides,
-                   llvm::SmallVector<int64_t, 4> hardwareSizes,
-                   llvm::SmallVector<int64_t, 4> hardwareStrides,
-                   bool skipTransformationChecks) {
+AIEX::verifyStridesWraps(mlir::Operation *forOp,
+                         mlir::MemRefType referencedBufType, int tileCol,
+                         int tileRow, llvm::SmallVector<int64_t, 4> inputSizes,
+                         llvm::SmallVector<int64_t, 4> inputStrides,
+                         llvm::SmallVector<int64_t, 4> hardwareSizes,
+                         llvm::SmallVector<int64_t, 4> hardwareStrides,
+                         bool skipTransformationChecks) {
   const auto &targetModel = AIE::getTargetModel(forOp);
   auto addressGranularity = targetModel.getAddressGenGranularity();
   auto elemWidth = referencedBufType.getElementTypeBitWidth();
@@ -244,11 +249,6 @@ verifyStridesWraps(mlir::Operation *forOp, mlir::MemRefType referencedBufType,
   return success();
 }
 
-} // namespace xilinx::AIEX
-
-#define GET_OP_CLASSES
-#include "aie/Dialect/AIEX/IR/AIEX.cpp.inc"
-
 //===----------------------------------------------------------------------===//
 // UseTokenOp
 //===----------------------------------------------------------------------===//