Remove old comments

Xilinx · Nov 19, 2024 · 3e108d7 · 3e108d7
1 parent 065866f
commit 3e108d7
Show file tree

Hide file tree

Showing 2 changed files with 1 addition and 5 deletions.
diff --git a/test/npu-xrt/adjacent_memtile_access/three_memtiles/aie2.py b/test/npu-xrt/adjacent_memtile_access/three_memtiles/aie2.py
@@ -16,7 +16,7 @@
 import numpy as np
 import sys
 
-from aie.dialects.aie import * # defines dma_wait (if I also import memref *, it also defines dma_wait -> the last one overwrittes other imports)
+from aie.dialects.aie import *
 from aie.dialects.aiex import *
 from aie.extras.context import mlir_mod_ctx
 from aie.helpers.dialects.ext.scf import _for as range_
@@ -193,8 +193,6 @@ def sequence(A, B, C):
             npu_dma_memcpy_nd(metadata="in1", bd_id=1, mem=A, sizes=[1, 1, 1, N])
             npu_dma_memcpy_nd(metadata="out", bd_id=0, mem=C, sizes=[1, 1, 1, N])
             npu_dma_wait("out")
-            #npu_sync(column=0, row=0, direction=0, channel=0)
-
 
 
 with mlir_mod_ctx() as ctx:

diff --git a/test/npu-xrt/adjacent_memtile_access/two_memtiles/aie2.py b/test/npu-xrt/adjacent_memtile_access/two_memtiles/aie2.py
@@ -166,8 +166,6 @@ def sequence(A, B, C):
             npu_dma_memcpy_nd(metadata="in1", bd_id=1, mem=A, sizes=[1, 1, 1, N])
             npu_dma_memcpy_nd(metadata="out", bd_id=0, mem=C, sizes=[1, 1, 1, N])
             npu_dma_wait("out")
-            #npu_sync(column=0, row=0, direction=0, channel=0)
-
 
 
 with mlir_mod_ctx() as ctx: