Fix lit paths

Xilinx · Nov 19, 2024 · 2f2ea9a · 2f2ea9a
1 parent 95897e3
commit 2f2ea9a
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/test/npu-xrt/adjacent_memtile_access/three_memtiles/aie2.py b/test/npu-xrt/adjacent_memtile_access/three_memtiles/aie2.py
@@ -9,7 +9,7 @@
 # REQUIRES: ryzen_ai
 #
 # RUN: %python %S/aie2.py > ./aie2.mlir
-# RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
+# RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt ./aie.mlir
 # RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags
 # RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s
 # CHECK: PASS!

diff --git a/test/npu-xrt/adjacent_memtile_access/two_memtiles/aie2.py b/test/npu-xrt/adjacent_memtile_access/two_memtiles/aie2.py
@@ -9,7 +9,7 @@
 # REQUIRES: ryzen_ai
 #
 # RUN: %python %S/aie2.py > ./aie2.mlir
-# RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
+# RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt ./aie.mlir
 # RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags
 # RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s
 # CHECK: PASS!