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restore int
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@makslevental
makslevental committed Nov 5, 2023
1 parent 3245eda commit 2ccf0ed
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Showing 23 changed files with 409 additions and 441 deletions.
90 changes: 45 additions & 45 deletions include/aie/Dialect/AIE/IR/AIE.td
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Original file line number Diff line number Diff line change
Expand Up @@ -130,10 +130,10 @@ def AIE_TileOp: AIE_Op<"tile", [FlowEndPoint]>, Results<(outs Index:$result)> {
}];

let extraClassDeclaration = [{
uint32_t getNumSourceConnections(WireBundle bundle);
uint32_t getNumDestConnections(WireBundle bundle);
uint32_t colIndex() { return getCol(); }
uint32_t rowIndex() { return getRow(); }
int getNumSourceConnections(WireBundle bundle);
int getNumDestConnections(WireBundle bundle);
int colIndex() { return getCol(); }
int rowIndex() { return getRow(); }
TileID getTileID() { return {getCol(), getRow()}; }
bool isShimTile() { return getRow() == 0; }
bool isMemTile();
Expand Down Expand Up @@ -166,7 +166,7 @@ def AIE_TileOp: AIE_Op<"tile", [FlowEndPoint]>, Results<(outs Index:$result)> {
let hasVerifier = 1;

let builders = [
OpBuilder<(ins "uint32_t":$col, "uint32_t":$row),
OpBuilder<(ins "int":$col, "int":$row),
[{
build($_builder, $_state, $_builder.getIndexType(),
$_builder.getI32IntegerAttr(col),
Expand Down Expand Up @@ -208,10 +208,10 @@ def AIE_SwitchboxOp: AIE_Op<"switchbox", [
let hasVerifier = 1;

let extraClassDeclaration = [{
uint32_t getNumSourceConnections(WireBundle bundle);
uint32_t getNumDestConnections(WireBundle bundle);
uint32_t colIndex();
uint32_t rowIndex();
int getNumSourceConnections(WireBundle bundle);
int getNumDestConnections(WireBundle bundle);
int colIndex();
int rowIndex();
TileOp getTileOp();
}];

Expand Down Expand Up @@ -275,10 +275,10 @@ def AIE_ShimMuxOp: AIE_Op<"shimmux", [
let hasVerifier = 1;

let extraClassDeclaration = [{
uint32_t colIndex();
uint32_t rowIndex();
uint32_t getNumSourceConnections(WireBundle bundle);
uint32_t getNumDestConnections(WireBundle bundle);
int colIndex();
int rowIndex();
int getNumSourceConnections(WireBundle bundle);
int getNumDestConnections(WireBundle bundle);
TileOp getTileOp();
}];

Expand Down Expand Up @@ -324,8 +324,8 @@ def AIE_ShimDMAOp: AIE_Op<"shimDMA", [
let hasVerifier = 1;

let extraClassDeclaration = [{
uint32_t colIndex();
uint32_t rowIndex();
int colIndex();
int rowIndex();
TileOp getTileOp();
static StringRef getDefaultDialect() { return "AIE"; }
}];
Expand Down Expand Up @@ -374,8 +374,8 @@ def AIE_CoreOp: AIE_Op<"core", [
let hasVerifier = 1;

let extraClassDeclaration = [{
uint32_t colIndex();
uint32_t rowIndex();
int colIndex();
int rowIndex();
bool isMemWest() { return ((rowIndex() % 2) == 0); };
TileOp getTileOp();
}];
Expand Down Expand Up @@ -407,7 +407,7 @@ def AIE_PLIOOp: AIE_Op<"plio", []>, Results<(outs Index)> {
let assemblyFormat = [{ `(` $col `)` attr-dict }];

let extraClassDeclaration = [{
uint32_t colIndex() { return getCol(); }
int colIndex() { return getCol(); }
}];
}

Expand Down Expand Up @@ -441,8 +441,8 @@ def AIE_ConnectOp: AIE_Op<"connect", [ParentOneOf<["SwitchboxOp", "ShimMuxOp"]>
}];

let extraClassDeclaration = [{
uint32_t sourceIndex() { return getSourceChannel(); }
uint32_t destIndex() { return getDestChannel(); }
int sourceIndex() { return getSourceChannel(); }
int destIndex() { return getDestChannel(); }
Port sourcePort() { return {getSourceBundle(), sourceIndex()}; }
Port destPort() { return {getDestBundle(), destIndex()}; }
}];
Expand Down Expand Up @@ -478,8 +478,8 @@ def AIE_FlowOp: AIE_Op<"flow", []> {
}];

let extraClassDeclaration = [{
uint32_t sourceIndex() { return getSourceChannel(); }
uint32_t destIndex() { return getDestChannel(); }
int sourceIndex() { return getSourceChannel(); }
int destIndex() { return getDestChannel(); }
}];
}

Expand Down Expand Up @@ -563,7 +563,7 @@ def AIE_MasterSetOp: AIE_Op<"masterset", [HasParent<"SwitchboxOp">]>, Results<(o
}];

let extraClassDeclaration = [{
uint32_t destIndex() { return getDestChannel(); }
int destIndex() { return getDestChannel(); }
Port destPort() { return {getDestBundle(), destIndex()}; }
}];
}
Expand Down Expand Up @@ -607,7 +607,7 @@ def AIE_PacketRulesOp: AIE_Op<"packetrules", [SingleBlockImplicitTerminator<"End
let hasVerifier = 1;

let extraClassDeclaration = [{
uint32_t sourceIndex() { return getSourceChannel(); }
int sourceIndex() { return getSourceChannel(); }
Port sourcePort() { return {getSourceBundle(), sourceIndex()}; }
}];
}
Expand Down Expand Up @@ -707,7 +707,7 @@ def AIE_PacketSourceOp: AIE_Op<"packet_source", [HasParent<"PacketFlowOp">]> {
}];

let extraClassDeclaration = [{
uint32_t channelIndex() { return getChannel(); }
int channelIndex() { return getChannel(); }
Port port() { return {getBundle(), channelIndex()}; }
}];
}
Expand All @@ -732,7 +732,7 @@ def AIE_PacketDestOp: AIE_Op<"packet_dest", [HasParent<"PacketFlowOp">]> {
}];

let extraClassDeclaration = [{
uint32_t channelIndex() { return getChannel(); }
int channelIndex() { return getChannel(); }
Port port() { return {getBundle(), channelIndex()}; }
}];
}
Expand Down Expand Up @@ -777,7 +777,7 @@ def AIE_DMABDPACKETOp: AIE_Op<"dmaBdPacket", []> {
}];

let extraClassDeclaration = [{
uint32_t getPacketID() { return getPacketId(); }
int getPacketID() { return getPacketId(); }
}];
}

Expand Down Expand Up @@ -882,15 +882,15 @@ def AIE_DMABDOp: AIE_Op<"dmaBd", []> {

let extraClassDeclaration = [{
BufferOp getBufferOp();
uint32_t getOffsetValue() { return getOffset(); }
uint32_t getLenValue() { return getLen(); }
int getOffsetValue() { return getOffset(); }
int getLenValue() { return getLen(); }
bool isA() { return (getAB() == 0); }
bool isB() { return (getAB() == 1); }
}];

let hasVerifier = 1;
let builders = [
OpBuilder<(ins "Value":$buffer, "uint32_t":$offset, "uint32_t":$len, "uint32_t":$AB), [{
OpBuilder<(ins "Value":$buffer, "int":$offset, "int":$len, "int":$AB), [{
odsState.addOperands(buffer);
odsState.addAttribute(getOffsetAttrName(odsState.name), $_builder.getI32IntegerAttr(offset));
odsState.addAttribute(getLenAttrName(odsState.name), $_builder.getI32IntegerAttr(len));
Expand Down Expand Up @@ -943,7 +943,7 @@ def AIE_DMAStartOp: AIE_Op<"dmaStart", [
}];

let builders = [
OpBuilder<(ins "DMAChannelDir":$channelDir, "uint32_t":$channelIndex, "Block *":$dest, "Block *":$chain),
OpBuilder<(ins "DMAChannelDir":$channelDir, "int":$channelIndex, "Block *":$dest, "Block *":$chain),
[{
build($_builder, $_state, $_builder.getIntegerType(1), channelDir, channelIndex, dest, chain);
}]>
Expand Down Expand Up @@ -984,10 +984,10 @@ def AIE_MemOp: AIE_Op<"mem", [
let hasVerifier = 1;

let extraClassDeclaration = [{
uint32_t colIndex();
uint32_t rowIndex();
int colIndex();
int rowIndex();
TileOp getTileOp();
uint32_t maxSizeInBytes() { return 32768; }
int maxSizeInBytes() { return 32768; }
// CallableOpInterface
Region *getCallableRegion();
ArrayRef<Type> getArgumentTypes() { return getOperand().getType(); }
Expand Down Expand Up @@ -1040,8 +1040,8 @@ def AIE_MemTileDMAOp: AIE_Op<"memTileDMA", [
let hasVerifier = 1;

let extraClassDeclaration = [{
uint32_t colIndex();
uint32_t rowIndex();
int colIndex();
int rowIndex();
TileOp getTileOp();
// CallableOpInterface
Region *getCallableRegion();
Expand Down Expand Up @@ -1132,12 +1132,12 @@ def AIE_LockOp: AIE_Op<"lock", [TileElement]>, Results<(outs Index)> {
}
llvm_unreachable("unreachable");
}
uint32_t getLockIDValue() {
int getLockIDValue() {
assert(getLockID().has_value() && "Lock has no ID value");
return getLockID().value();
}
uint32_t colIndex();
uint32_t rowIndex();
int colIndex();
int rowIndex();
TileOp getTileOp();
}];

Expand Down Expand Up @@ -1188,8 +1188,8 @@ def AIE_UseLockOp: AIE_Op<"useLock", []> {
bool acquire() { return (getAction() == LockAction::Acquire); }
bool acquire_ge() { return (getAction() == LockAction::AcquireGreaterEqual); }
bool release() { return (getAction() == LockAction::Release); }
uint32_t getLockValue() { return getValue(); }
uint32_t getTimeout() { if(auto val = getBlocking()) return (int)*val; else return 1;}
int getLockValue() { return getValue(); }
int getTimeout() { if(auto val = getBlocking()) return (int)*val; else return 1;}
LockOp getLockOp() { return dyn_cast<xilinx::AIE::LockOp>(getLock().getDefiningOp()); }
}];
}
Expand Down Expand Up @@ -1504,7 +1504,7 @@ def AIE_ObjectFifoCreateOp: AIE_Op<"objectFifo", [HasParent<"DeviceOp">, Symbol]
let hasVerifier = 1;

let extraClassDeclaration = [{
uint32_t size( uint32_t index = 0) {
int size(int index = 0) {
if (isa<ArrayAttr>(getElemNumber()))
return dyn_cast<IntegerAttr>(dyn_cast<ArrayAttr>(getElemNumber())[index]).getInt();
else
Expand Down Expand Up @@ -1669,7 +1669,7 @@ def AIE_ObjectFifoAcquireOp: AIE_Op<"objectFifo.acquire", []> {

let extraClassDeclaration = [{
ObjectFifoCreateOp getObjectFifo();
uint32_t acqNumber() { return getSize(); }
int acqNumber() { return getSize(); }
}];
}

Expand Down Expand Up @@ -1703,7 +1703,7 @@ def AIE_ObjectFifoReleaseOp: AIE_Op<"objectFifo.release", []> {

let extraClassDeclaration = [{
ObjectFifoCreateOp getObjectFifo();
uint32_t relNumber() { return getSize(); }
int relNumber() { return getSize(); }
}];
}

Expand Down Expand Up @@ -1805,7 +1805,7 @@ def AIE_ObjectFifoRegisterProcessOp: AIE_Op<"objectFifo.registerProcess", []> {
.cast<DenseIntElementsAttr>();
}

uint32_t getProcessLength() {
int getProcessLength() {
return getLength()
.getDefiningOp<arith::ConstantOp>()
.getValue()
Expand Down
8 changes: 4 additions & 4 deletions include/aie/Dialect/AIE/IR/AIEDialect.h
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Original file line number Diff line number Diff line change
Expand Up @@ -150,7 +150,7 @@ namespace AIE {

typedef struct Port {
WireBundle bundle;
uint32_t channel;
int channel;

inline bool operator==(const Port &rhs) const {
return std::tie(bundle, channel) == std::tie(rhs.bundle, rhs.channel);
Expand All @@ -175,7 +175,7 @@ typedef struct Connect {

typedef struct DMAChannel {
DMAChannelDir direction;
uint32_t channel;
int channel;

inline bool operator==(const DMAChannel &rhs) const {
return std::tie(direction, channel) == std::tie(rhs.direction, rhs.channel);
Expand Down Expand Up @@ -280,7 +280,7 @@ template <> struct DenseMapInfo<ObjectFifoCreateOp> {

template <> struct DenseMapInfo<DMAChannel> {
using FirstInfo = DenseMapInfo<DMAChannelDir>;
using SecondInfo = DenseMapInfo<uint32_t>;
using SecondInfo = DenseMapInfo<int>;
static inline DMAChannel getEmptyKey() {
return {FirstInfo::getEmptyKey(), SecondInfo::getEmptyKey()};
}
Expand All @@ -301,7 +301,7 @@ template <> struct DenseMapInfo<DMAChannel> {

template <> struct DenseMapInfo<Port> {
using FirstInfo = DenseMapInfo<WireBundle>;
using SecondInfo = DenseMapInfo<uint32_t>;
using SecondInfo = DenseMapInfo<int>;
static inline Port getEmptyKey() {
return {FirstInfo::getEmptyKey(), SecondInfo::getEmptyKey()};
}
Expand Down
12 changes: 6 additions & 6 deletions include/aie/Dialect/AIE/IR/AIEInterfaces.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,10 +49,10 @@ def FlowEndPoint : OpInterface<"FlowEndPoint"> {
let cppNamespace = "::xilinx::AIE";
let methods = [
InterfaceMethod<[{}],
"uint32_t", "colIndex", (ins )
"int", "colIndex", (ins )
>,
InterfaceMethod<[{}],
"uint32_t", "rowIndex", (ins )
"int", "rowIndex", (ins )
>
];
}
Expand All @@ -69,16 +69,16 @@ def Interconnect : OpInterface<"Interconnect"> {
"::mlir::Region &", "getConnections", (ins )
>,
InterfaceMethod<[{}],
"uint32_t", "colIndex", (ins )
"int", "colIndex", (ins )
>,
InterfaceMethod<[{}],
"uint32_t", "rowIndex", (ins )
"int", "rowIndex", (ins )
>,
InterfaceMethod<[{}],
"uint32_t", "getNumSourceConnections", (ins "WireBundle":$bundle)
"int", "getNumSourceConnections", (ins "WireBundle":$bundle)
>,
InterfaceMethod<[{}],
"uint32_t", "getNumDestConnections", (ins "WireBundle":$bundle)
"int", "getNumDestConnections", (ins "WireBundle":$bundle)
>
];
}
Expand Down
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