Merge branch 'main' of https://github.com/Xilinx/mlir-aie into colorD…

…etect

.github/workflows/buildAndTestRyzenAI.yml

@@ -0,0 +1,61 @@
+name: Build and Test with AIE tools on Ryzen AI
+
+on:
+  push:
+    branches:
+      - main
+      - test-ryzen-ai
+  workflow_dispatch:
+
+defaults:
+  run:
+    shell: bash
+
+env:
+  DEBIAN_FRONTEND: noninteractive
+  XILINXD_LICENSE_FILE: /opt/xilinx/Xilinx.lic
+
+jobs:
+  build-repo:
+    name: Build and Test
+
+    runs-on: amd7940hs
+
+    steps:
+
+      - uses: actions/checkout@v3
+        with:
+          submodules: "true"
+
+      - name: Run commands
+        run: |
+
+            python -m venv aie-venv
+            source aie-venv/bin/activate
+            pip install -r utils/requirements.txt
+            pip install lit
+
+            pip -q download mlir -f https://makslevental.github.io/wheels && unzip -q mlir-18*.whl
+
+            mkdir build
+            cd build
+
+            export PATH=/opt/Xilinx/Vitis/2023.2/bin:/opt/Xilinx/Vitis/2023.2/aietools/bin:$PATH
+            cmake .. -G Ninja \
+              -DMLIR_DIR=$PWD/../mlir/lib/cmake/mlir \
+              -DCMAKE_MODULE_PATH=$PWD/../cmake/modulesXilinx \
+              -DLLVM_EXTERNAL_LIT=$(which lit) \
+              -DAIE_INCLUDE_INTEGRATION_TESTS=OFF \
+              -DCMAKE_EXE_LINKER_FLAGS_INIT="-fuse-ld=lld" \
+              -DCMAKE_MODULE_LINKER_FLAGS_INIT="-fuse-ld=lld" \
+              -DCMAKE_SHARED_LINKER_FLAGS_INIT="-fuse-ld=lld" \
+              -DCMAKE_C_COMPILER_LAUNCHER=ccache \
+              -DCMAKE_CXX_COMPILER_LAUNCHER=ccache \
+              -DXRT_ROOT=/opt/xilinx/xrt \
+              -DAIE_ENABLE_PYTHON_PASSES=OFF \
+              -DCMAKE_INSTALL_PREFIX=install
+
+            ninja install
+
+            sed -i.bak 's/-sv --timeout 600/-sv --timeout 600 -j12 --show-unsupported/g' $PWD/../test/CMakeLists.txt
+            ninja check-aie

reference_designs/CMakeLists.txt

@@ -68,6 +68,8 @@ set(MLIR_BINARY_DIR ${CMAKE_BINARY_DIR})
 
 find_package(Vitis 2023.2 COMPONENTS AIE AIE2)
 find_package(Python3 COMPONENTS Interpreter)
+find_package(XRT)
+find_package(OpenCV)
 
 # Look for LibXAIE
 if (DEFINED LibXAIE_${AIE_RUNTIME_TEST_TARGET}_DIR)

reference_designs/ipu-xrt/add_one_objFifo/run.lit

@@ -1,5 +1,10 @@
 // (c) Copyright 2023 Advanced Micro Devices, Inc.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// REQUIRES: ryzen_ai
+//
 // RUN: %python %S/aie2.py > ./aie.mlir
-// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=final.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=aie.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
+// RUN: %run_on_ipu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s
+// CHECK: PASS!

reference_designs/ipu-xrt/log_hello_world/run.lit

@@ -1,6 +1,12 @@
 // (c) Copyright 2023 Advanced Micro Devices, Inc.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// REQUIRES: ryzen_ai
+//
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -c %S/kernel.cc -o ./kernel.o
 // RUN: %python %S/hello_world.py > ./aie.mlir
-// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=final.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=aie.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
+// RUN: %python %S/elfStringParser.py --input . --output elf_string.csv
+// RUN: %run_on_ipu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt -e elf_string.csv
+// CHECK: PASS!

reference_designs/ipu-xrt/matrix_multiplication/run.lit

@@ -1,6 +1,11 @@
 // (c) Copyright 2023 Advanced Micro Devices, Inc.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// REQUIRES: ryzen_ai
+//
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -c %S/mm.cc -o ./mm.o
 // RUN: %python %S/aie2.py > ./aie.mlir
-// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=final.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=aie.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
+// RUN: %run_on_ipu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s
+// CHECK: PASS!

reference_designs/ipu-xrt/passthrough_hardware/run.lit

@@ -1,5 +1,10 @@
 // (c) Copyright 2023 Advanced Micro Devices, Inc.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// REQUIRES: ryzen_ai
+//
 // RUN: %python %S/aie2.py > ./aie.mlir
-// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=final.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=aie.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
+// RUN: %run_on_ipu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt -l 4096
+// CHECK: PASS!

reference_designs/ipu-xrt/vector_scalar/run.lit

@@ -1,6 +1,11 @@
 // (c) Copyright 2023 Advanced Micro Devices, Inc.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// REQUIRES: ryzen_ai
+//
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -c %S/scale.cc -o ./scale.o
 // RUN: %python %S/aie2.py > ./aie.mlir
-// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=final.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=aie.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
+// RUN: %run_on_ipu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s
+// CHECK: PASS!

reference_designs/ipu-xrt/vision_pipelines/color_threshold/README.md

@@ -17,7 +17,7 @@ The pipeline is mapped onto a single column of the ipu device, with one Shim til
 <p align="center">
   <img
     src="./color_threshold_pipeline.png"
-    width="850">
+    width="750">
 </p>
 
 The data movement of this pipeline is described using the OrderedObjectBuffer (OOB) primitive. The input image is brought into the array via Shim tile (0, 0) and first sent to Mem tile (0, 1). There it is split into smaller blocks of data and each block is distributed to one of the 4 AIE tiles (0, 2) to (0, 5). One OOB is used to express data movement from the Shim tile to the Mem tile. Four different OOBs express the one-to-one data movements between the Mem tile and each of the compute tiles. The input OOB is linked to the other four OOBs to express that data from the input OOB should be copied implicitly to the other OOBs via the DMA. Currently, the ordering of the four OOBs in the Link operation expresses what piece of input data should go to each compute tile.

reference_designs/ipu-xrt/vision_pipelines/edge_detect/README.md

@@ -17,7 +17,7 @@ The pipeline is mapped onto a single column of the ipu device, with one Shim til
 <p align="center">
   <img
     src="./edge_detect_pipeline.png"
-    width="900">
+    width="1050">
 </p>
 
 The data movement of this pipeline is described using the OrderedObjectBuffer (OOB) primitive. Input data is brought into the array via the Shim tile. The data then needs to be broadcasted both to AIE tile (0, 2) and AIE tile (0, 5). However, tile (0, 5) has to wait for additional data from the other kernels before it can proceed with its execution, so in order to avoid any stalls in the broadcast, data for tile (0, 5) is instead buffered in the Mem tile. Because of the size of the data, the buffering couldn't directly be done in the smaller L1 memory module of tile (0, 5). This is described using two OOBs, one for the broadcast to tile (0, 2) and the Mem tile, and one for the data movement between the Mem tile and tile (0, 5). The two OOBs are linked to express that data from the first OOB should be copied to the second OOB implicitly through the Mem tile's DMA.

reference_designs/ipu-xrt/vision_pipelines/edge_detect/run.lit

@@ -1,11 +1,16 @@
 // (c) Copyright 2023 Advanced Micro Devices, Inc.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
+// REQUIRES: ryzen_ai, opencv
+//
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -DBIT_WIDTH=8 -c %S/../vision_kernels/rgba2gray.cc -o ./rgba2gray.cc.o
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -DBIT_WIDTH=8 -c %S/../vision_kernels/gray2rgba.cc -o ./gray2rgba.cc.o
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -DBIT_WIDTH=8 -c %S/../vision_kernels/threshold.cc -o ./threshold.cc.o
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -DBIT_WIDTH=8 -c %S/../vision_kernels/addWeighted.cc -o ./addWeighted.cc.o
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -DBIT_WIDTH=8 -c %S/../vision_kernels/filter2d.cc -o ./filter2d.cc.o
 // RUN: ar rvs combined_gray2rgba_addWeighted.a gray2rgba.cc.o addWeighted.cc.o
-// RUN: %python %S/aie2_edgeDetect.py > ./aie.mlir
-// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=final.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: %python %S/aie2_edgeDetect.py 64 36 > ./aie.mlir
+// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=aie.xclbin --ipu-insts-name=insts.txt ./aie.mlir
+// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -DEDGEDETECT_WIDTH=64 -DEDGEDETECT_HEIGHT=36 -I %S/../../../utils %S/../../../utils/xrtUtils.cpp %S/../../../utils/OpenCVUtils.cpp %opencv_flags -lboost_program_options -lboost_filesystem 
+// RUN: %run_on_ipu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s
+// CHECK: PASS!

reference_designs/lit.cfg.py

@@ -56,6 +56,46 @@
 else:
     config.substitutions.append(("%run_on_board", "echo"))
 
+run_on_ipu = "echo"
+xrt_flags = ""
+if config.xrt_lib_dir:
+    print("xrt found at", os.path.dirname(config.xrt_lib_dir))
+    xrt_flags = "-I{} -L{} -luuid -lxrt_coreutil".format(
+        config.xrt_include_dir, config.xrt_lib_dir
+    )
+    try:
+        xbutil = os.path.join(config.xrt_bin_dir, "xbutil")
+        result = subprocess.run(
+            [xbutil, "examine"], stdout=subprocess.PIPE, stderr=subprocess.PIPE
+        )
+        result = result.stdout.decode("utf-8").split("\n")
+        p = re.compile("\[.+:.+:.+\].+Phoenix.+Yes")
+        for l in result:
+            m = p.match(l)
+            if m:
+                print("Found Ryzen AI device:", m.group().split()[0])
+                config.available_features.add("ryzen_ai")
+                run_on_ipu = "flock /tmp/ipu.lock /opt/xilinx/run_on_ipu.sh"
+    except:
+        print("Failed to run xbutil")
+        pass
+else:
+    print("xrt not found")
+config.substitutions.append(("%run_on_ipu", run_on_ipu))
+config.substitutions.append(("%xrt_flags", xrt_flags))
+
+opencv_flags = ""
+if config.opencv_include_dir and config.opencv_libs:
+    config.available_features.add("opencv")
+    opencv_flags = opencv_flags + " -I" + config.opencv_include_dir
+    if config.opencv_lib_dir:
+        opencv_flags = opencv_flags + " -L" + config.opencv_lib_dir
+    libs = config.opencv_libs.split(";")
+    opencv_flags = opencv_flags + " " + " ".join(["-l" + l for l in libs])
+else:
+    opencv_flags = ""
+config.substitutions.append(("%opencv_flags", opencv_flags))
+
 VitisSysrootFlag = ""
 if config.aieHostTarget == "x86_64":
     config.substitutions.append(("%aieHostTargetTriplet%", "x86_64-unknown-linux-gnu"))

reference_designs/lit.site.cfg.py.in

@@ -37,6 +37,12 @@ config.host_ldflags = '@HOST_LDFLAGS@'
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.llvm_host_triple = '@LLVM_HOST_TRIPLE@'
 config.host_arch = "@HOST_ARCH@"
+config.xrt_bin_dir = "@XRT_BIN_DIR@"
+config.xrt_lib_dir = "@XRT_LIB_DIR@"
+config.xrt_include_dir = "@XRT_INCLUDE_DIR@"
+config.opencv_libs = "@OpenCV_LIBS@"
+config.opencv_lib_dir = "@OpenCV_LIB_PATH@"
+config.opencv_include_dir = "@OpenCV_INCLUDE_DIRS@"
 
 config.aie_src_root = "@AIE_SOURCE_DIR@"
 config.aie_obj_root = "@AIE_BINARY_DIR@"

test/CMakeLists.txt

@@ -59,6 +59,7 @@ set(MLIR_BINARY_DIR ${CMAKE_BINARY_DIR})
 
 find_package(Vitis 2023.2 COMPONENTS AIE AIE2)
 find_package(Python3 COMPONENTS Interpreter)
+find_package(XRT)
 
 cmake_dependent_option(ENABLE_CHESS_TESTS "Enable backend tests using xchesscc" ON "Vitis_FOUND" OFF)
 cmake_dependent_option(ENABLE_BOARD_TESTS "Enable board tests" ON "CMAKE_HOST_SYSTEM_PROCESSOR MATCHES aarch64" OFF)

test/ipu-xrt/add_one_objFifo/run.lit

@@ -1,4 +1,8 @@
 // (c) Copyright 2023 Advanced Micro Devices, Inc.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// RUN: %python aiecc.py --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=final.xclbin --ipu-insts-name=insts.txt %S/aie.mlir
+// REQUIRES: ryzen_ai
+//
+// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=final.xclbin --ipu-insts-name=insts.txt %S/aie.mlir
+// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
+// RUN: %run_on_ipu ./test.exe -x final.xclbin -k MLIR_AIE -i insts.txt

test/lit.cfg.py

@@ -60,6 +60,34 @@
 else:
     config.substitutions.append(("%run_on_board", "echo"))
 
+run_on_ipu = "echo"
+xrt_flags = ""
+if config.xrt_lib_dir:
+    print("xrt found at", os.path.dirname(config.xrt_lib_dir))
+    xrt_flags = "-I{} -L{} -luuid -lxrt_coreutil".format(
+        config.xrt_include_dir, config.xrt_lib_dir
+    )
+    try:
+        xbutil = os.path.join(config.xrt_bin_dir, "xbutil")
+        result = subprocess.run(
+            [xbutil, "examine"], stdout=subprocess.PIPE, stderr=subprocess.PIPE
+        )
+        result = result.stdout.decode("utf-8").split("\n")
+        p = re.compile("\[.+:.+:.+\].+Phoenix.+Yes")
+        for l in result:
+            m = p.match(l)
+            if m:
+                print("Found Ryzen AI device:", m.group().split()[0])
+                config.available_features.add("ryzen_ai")
+                run_on_ipu = "flock /tmp/ipu.lock /opt/xilinx/run_on_ipu.sh"
+    except:
+        print("Failed to run xbutil")
+        pass
+else:
+    print("xrt not found")
+config.substitutions.append(("%run_on_ipu", run_on_ipu))
+config.substitutions.append(("%xrt_flags", xrt_flags))
+
 VitisSysrootFlag = ""
 if config.aieHostTarget == "x86_64":
     config.substitutions.append(("%aieHostTargetTriplet%", "x86_64-unknown-linux-gnu"))

test/lit.site.cfg.py.in

@@ -38,6 +38,9 @@ config.host_ldflags = '@HOST_LDFLAGS@'
 config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@"
 config.llvm_host_triple = '@LLVM_HOST_TRIPLE@'
 config.host_arch = "@HOST_ARCH@"
+config.xrt_bin_dir = "@XRT_BIN_DIR@"
+config.xrt_lib_dir = "@XRT_LIB_DIR@"
+config.xrt_include_dir = "@XRT_INCLUDE_DIR@"
 
 config.aie_src_root = "@AIE_SOURCE_DIR@"
 config.aie_obj_root = "@AIE_BINARY_DIR@"

test/unit_tests/aie/29_aie2_nd_dma_even_odd/aie.mlir

@@ -26,7 +26,7 @@
 // REQUIRES: valid_xchess_license
 // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test -L%host_runtime_lib%/test_lib/lib -ltest_lib
 // RUN: %run_on_board ./test.elf
-// RUN: aie.mlir.prj/aiesim.sh | FileCheck %s
+// RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s
 
 // CHECK: AIE2 ISS
 // CHECK: PASS!

test/unit_tests/aie/30_aie2_nd_dma_transpose_repeat/aie.mlir

@@ -14,7 +14,7 @@
 // REQUIRES: valid_xchess_license
 // RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% %S/test.cpp -o test -L%host_runtime_lib%/test_lib/lib -ltest_lib
 // RUN: %run_on_board ./test.elf
-// RUN: aie.mlir.prj/aiesim.sh | FileCheck %s
+// RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s
 
 // CHECK: AIE2 ISS
 // CHECK: PASS!

test/unit_tests/aie/31_stream_core/aie.mlir

@@ -14,6 +14,8 @@
 // CHECK: test start.
 // CHECK: PASS!
 
+// XFAIL: *
+
 module {
   %tile13 = AIE.tile(1, 3)
   %tile23 = AIE.tile(2, 3)

test/unit_tests/aie2/04_shared_memory/aie_row.mlir

@@ -18,23 +18,23 @@
 
 module @test04_shared_memory {
   AIE.device(xcve2802) {
-    %tile13 = AIE.tile(1, 3)
     %tile23 = AIE.tile(2, 3)
+    %tile33 = AIE.tile(3, 3)
 
-    %buf13_0 = AIE.buffer(%tile13) { sym_name = "a" } : memref<256xi32>
-    %buf13_1 = AIE.buffer(%tile13) { sym_name = "b" } : memref<256xi32>
-    %buf23_0 = AIE.buffer(%tile23) { sym_name = "c" } : memref<256xi32>
+    %buf13_0 = AIE.buffer(%tile23) { sym_name = "a" } : memref<256xi32>
+    %buf13_1 = AIE.buffer(%tile23) { sym_name = "b" } : memref<256xi32>
+    %buf23_0 = AIE.buffer(%tile33) { sym_name = "c" } : memref<256xi32>
 
-    %lock13_2 = AIE.lock(%tile13, 2) { sym_name = "test_lock" } // test lock
+    %lock13_2 = AIE.lock(%tile23, 2) { sym_name = "test_lock" } // test lock
 
-    %lock13_3 = AIE.lock(%tile13, 3) { sym_name = "input_write_lock", init = 1 : i32 } // input buffer lock
-    %lock13_4 = AIE.lock(%tile13, 4) { sym_name = "input_read_lock" } // input buffer lock
-    %lock13_5 = AIE.lock(%tile13, 5) { sym_name = "hidden_write_lock", init = 1 : i32 } // interbuffer lock
-    %lock13_6 = AIE.lock(%tile13, 6) { sym_name = "hidden_read_lock" } // interbuffer lock
-    %lock23_7 = AIE.lock(%tile23, 7) { sym_name = "output_write_lock", init = 1 : i32 } // output buffer lock
-    %lock23_8 = AIE.lock(%tile23, 8) { sym_name = "output_read_lock" } // output buffer lock
+    %lock13_3 = AIE.lock(%tile23, 3) { sym_name = "input_write_lock", init = 1 : i32 } // input buffer lock
+    %lock13_4 = AIE.lock(%tile23, 4) { sym_name = "input_read_lock" } // input buffer lock
+    %lock13_5 = AIE.lock(%tile23, 5) { sym_name = "hidden_write_lock", init = 1 : i32 } // interbuffer lock
+    %lock13_6 = AIE.lock(%tile23, 6) { sym_name = "hidden_read_lock" } // interbuffer lock
+    %lock23_7 = AIE.lock(%tile33, 7) { sym_name = "output_write_lock", init = 1 : i32 } // output buffer lock
+    %lock23_8 = AIE.lock(%tile33, 8) { sym_name = "output_read_lock" } // output buffer lock
 
-    %core13 = AIE.core(%tile13) {
+    %core13 = AIE.core(%tile23) {
       AIE.useLock(%lock13_4, AcquireGreaterEqual, 1) // acquire input for read(e.g. input ping)
       AIE.useLock(%lock13_5, AcquireGreaterEqual, 1) // acquire input for write
       %idx1 = arith.constant 3 : index
@@ -50,7 +50,7 @@ module @test04_shared_memory {
       AIE.end
     }
 
-    %core23 = AIE.core(%tile23) {
+    %core23 = AIE.core(%tile33) {
       AIE.useLock(%lock13_6, AcquireGreaterEqual, 1) // acquire input for read(e.g. input ping)
       AIE.useLock(%lock23_7, AcquireGreaterEqual, 1) // acquire output for write
       %idx1 = arith.constant 5 : index

test/unit_tests/chess_compiler_tests/00_itsalive/aie.mlir

@@ -9,6 +9,7 @@
 //===----------------------------------------------------------------------===//
 
 // REQUIRES: valid_xchess_license
+// REQUIRES: peano
 // RUN: %PYTHON aiecc.py --no-unified --xchesscc    --xbridge %s
 // RUN: %PYTHON aiecc.py --unified    --xchesscc    --xbridge %s
 // RUN: %PYTHON aiecc.py --no-unified --no-xchesscc --xbridge %s