Merge pull request #740 from rstar900/feature/ultra96v2-support

Feature/ultra96v2 support
Xilinx · Nov 7, 2023 · fe9e969 · fe9e969
2 parents a0a0586 + 3c40245
commit fe9e969
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diff --git a/src/finn/transformation/fpgadataflow/templates.py b/src/finn/transformation/fpgadataflow/templates.py
@@ -120,6 +120,9 @@
 } elseif {$BOARD == "Ultra96"} {
     set_property board_part avnet.com:ultra96v1:part0:1.2 [current_project]
     set ZYNQ_TYPE "zynq_us+"
+} elseif {$BOARD == "Ultra96-V2"} {
+    set_property board_part avnet.com:ultra96v2:part0:1.2 [current_project]
+    set ZYNQ_TYPE "zynq_us+"
 } elseif {$BOARD == "Pynq-Z2"} {
     set ZYNQ_TYPE "zynq_7000"
     set_property board_part tul.com.tw:pynq-z2:part0:1.0 [current_project]

diff --git a/src/finn/util/basic.py b/src/finn/util/basic.py
@@ -37,6 +37,7 @@
 # mapping from PYNQ board names to FPGA part names
 pynq_part_map = dict()
 pynq_part_map["Ultra96"] = "xczu3eg-sbva484-1-e"
+pynq_part_map["Ultra96-V2"] = "xczu3eg-sbva484-1-i"
 pynq_part_map["Pynq-Z1"] = "xc7z020clg400-1"
 pynq_part_map["Pynq-Z2"] = "xc7z020clg400-1"
 pynq_part_map["ZCU102"] = "xczu9eg-ffvb1156-2-e"
@@ -51,6 +52,7 @@
 pynq_native_port_width["Pynq-Z1"] = 64
 pynq_native_port_width["Pynq-Z2"] = 64
 pynq_native_port_width["Ultra96"] = 128
+pynq_native_port_width["Ultra96-V2"] = 128
 pynq_native_port_width["ZCU102"] = 128
 pynq_native_port_width["ZCU104"] = 128
 pynq_native_port_width["ZCU111"] = 128