[pyxsi] Import optional to ensure non synthesis tests run

Xilinx · Nov 19, 2024 · 42582f9 · 42582f9
1 parent bf1fafa
commit 42582f9
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Showing 4 changed files with 18 additions and 4 deletions.
diff --git a/src/finn/core/rtlsim_exec.py b/src/finn/core/rtlsim_exec.py
@@ -46,7 +46,10 @@
 except ModuleNotFoundError:
     PyVerilator = None
 
-import pyxsi_utils
+try:
+    import pyxsi_utils
+except ModuleNotFoundError:
+    pyxsi_utils = None
 
 
 def prep_rtlsim_io_dict(model, execution_context):

diff --git a/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py b/src/finn/custom_op/fpgadataflow/hls/addstreams_hls.py
@@ -28,12 +28,16 @@
 
 import numpy as np
 import os
-import pyxsi_utils
 
 from finn.custom_op.fpgadataflow.addstreams import AddStreams
 from finn.custom_op.fpgadataflow.hlsbackend import HLSBackend
 from finn.util.data_packing import npy_to_rtlsim_input, rtlsim_output_to_npy
 
+try:
+    import pyxsi_utils
+except ModuleNotFoundError:
+    pyxsi_utils = None
+
 
 class AddStreams_hls(AddStreams, HLSBackend):
     """Class that corresponds to finn-hlslib AddStreams_Batch function."""

diff --git a/src/finn/custom_op/fpgadataflow/hlsbackend.py b/src/finn/custom_op/fpgadataflow/hlsbackend.py
@@ -28,7 +28,6 @@
 
 import numpy as np
 import os
-import pyxsi_utils
 import subprocess
 from abc import ABC, abstractmethod
 from qonnx.core.datatype import DataType
@@ -43,6 +42,11 @@
 except ModuleNotFoundError:
     PyVerilator = None
 
+try:
+    import pyxsi_utils
+except ModuleNotFoundError:
+    pyxsi_utils = None
+
 
 class HLSBackend(ABC):
     """HLSBackend class all custom ops that correspond to a finn-hlslib

diff --git a/src/finn/custom_op/fpgadataflow/hwcustomop.py b/src/finn/custom_op/fpgadataflow/hwcustomop.py
@@ -41,7 +41,10 @@
 except ModuleNotFoundError:
     PyVerilator = None
 
-import pyxsi_utils
+try:
+    import pyxsi_utils
+except ModuleNotFoundError:
+    pyxsi_utils = None
 
 
 class HWCustomOp(CustomOp):