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36 Open 19 Closed
36 Open 19 Closed
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Issues list

Check code quality in a continuous way
#74 opened Sep 20, 2024 by racodond
4
Vivado configuration fails
#73 opened Aug 29, 2023 by poneill1001
1
Please update link to OSVVM
#72 opened Jun 8, 2023 by JimLewis
CYCLONE II FPGA with TM1638 in VHDL code Help Wanted
#71 opened Mar 24, 2023 by paskalthelordoffpga
3
Failed to configure
#70 opened Nov 1, 2022 by albydnc
3
Is this library being maintained? Question
#69 opened Jul 13, 2022 by harry-commin-enclustra
@Paebbels
1
GHDL VHDL -> Yosys code for BLOCKRAM (used as ROM)
#68 opened Jan 8, 2022 by PPlinux
Error during configuration
#67 opened Sep 14, 2020 by mbieker
2
"misc_strobegenerator" is missing
#63 opened Dec 11, 2018 by rhentges
configuration problem Bug Project: Infrastructure
#62 opened Oct 26, 2018 by sasamy1
@Paebbels
6
Submodules are not up-to-date Bug
#58 opened Jul 6, 2018 by FranzForstmayr
@Paebbels
7
fifo_dc_got.vhdl is missing Bug
#56 opened Mar 5, 2018 by rhentges
configuration crashes at Intel Modelsim setup Bug
#49 opened Aug 31, 2017 by jobermueller Version 1.2
@Paebbels
5
Error for string.vhdl - Value := resize(slv, Value'length); Bug
#48 opened Aug 18, 2017 by bhamadicharef
@preusser
8
Doc: Document the change log from v0.0.0 until now Project: Documentation
#45 opened Dec 19, 2016 by Paebbels Version 1.2
@Paebbels
PyInfra: Add tool support for Aldec Riviera-PRO Help Wanted Project: Infrastructure
#44 opened Dec 19, 2016 by Paebbels
15 tasks
Version 1.3
@Paebbels
Rewrite testbenches and simulation packages for VHDL-2008 only. Project: Packages Project: Testbench
#43 opened Dec 19, 2016 by Paebbels
14 tasks
Version 1.3
@Paebbels @mzabeltud
Doc: Document installed Sphinx extensions, usable syntax, modifications Project: Documentation
#42 opened Dec 18, 2016 by Paebbels
14 tasks
Version 1.3
@Paebbels
Doc: Document Python dependencies in the Quick Start Guide Project: Documentation
#41 opened Dec 15, 2016 by Paebbels
1 of 8 tasks
Version 1.2
@Paebbels
PyInfra: Add tool support for Xilinx Vivado IP Catalog Enhancement Project: Infrastructure
#40 opened Dec 3, 2016 by Paebbels Version 1.3
@Paebbels
PyInfra: Add tool support for Synopsys Synplify Pro Enhancement Project: Infrastructure
#39 opened Dec 3, 2016 by Paebbels Version 1.3
@Paebbels
2
PyInfra: Add tool support for Mentor Graphics Precision-RTL Enhancement Project: Infrastructure
#38 opened Dec 3, 2016 by Paebbels Someday Maybe
@Paebbels
PyInfra: Add tool support for Cadence Incisive Enhancement Project: Infrastructure
#37 opened Dec 3, 2016 by Paebbels Version 1.x
@Paebbels
PyInfra: Calculate compile order of VHDL files. Enhancement Project: Infrastructure
#36 opened Dec 3, 2016 by Paebbels Version 1.x
@Paebbels
PyInfra: Provide a PowerShell drive Enhancement Project: Infrastructure
#35 opened Dec 3, 2016 by Paebbels Someday Maybe
ProTip! Exclude everything labeled bug with -label:bug.