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Add AXIS Cache IP, FPGA code housekeeping, etc. #826

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Add AXIS Cache IP, FPGA code housekeeping, etc. #826

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d0a7b88
fpga: Add driver for new register interface of axis cache IP
n-eiling Oct 27, 2024
a62a9e4
fpga: Add new Dino configuration register that allows triggering the …
n-eiling Oct 27, 2024
63e498a
fpga: Add axis_cache.cpp to CMakeLists.txt
n-eiling Oct 27, 2024
9d693fb
fpga: Fix I2c causing an error when Dino FMC is not connected. We loo…
n-eiling Oct 27, 2024
e8cf0f7
hooks: Cast hook should also work for writes.
n-eiling Oct 27, 2024
2f48f6d
fpga: Clean up dino.cpp
n-eiling Oct 27, 2024
8e6ec16
fpga/ips: add invalidate method to AxisCache and whitelist the IP in …
n-eiling Oct 31, 2024
157a943
fpga: improve comments
n-eiling Nov 4, 2024
24a28a5
fpga: consolidate and update FPGA config examples
n-eiling Nov 4, 2024
6a8b138
fpga/ip/i2c: remove dead code and improve comment.
n-eiling Nov 4, 2024
c44d3c6
fpga: Apply suggestions from code review
n-eiling Nov 5, 2024
8ce4824
fpga: improve code style
n-eiling Nov 5, 2024
ae5efeb
fpga: remove exceptions from AxisCache
n-eiling Nov 11, 2024
a896675
fpga: fix configCrossBar crashing if src or dest are nullptr
n-eiling Nov 15, 2024
2571ec9
fpga: add dinoif_adc to hwdef-parse.py
n-eiling Nov 15, 2024
ebd1036
fpga: update example jsons
n-eiling Nov 15, 2024
356c099
fpga: make hwdef-parse.py correctly detect interrupt on zynq designs
n-eiling Dec 2, 2024
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2 changes: 1 addition & 1 deletion etc/examples/nodes/fpga.conf
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ fpgas = {
id = "10ee:7021"
slot = "0000:88:00.0"
do_reset = true
ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino-v2.json"
ips = "../../fpga/etc/vc707-xbar-pcie/vc707-xbar-pcie-dino.json"
polling = false
}
}
Expand Down
83 changes: 66 additions & 17 deletions etc/fpga/vc707-xbar-pcie-dino/vc707-xbar-pcie-dino.json
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Original file line number Diff line number Diff line change
Expand Up @@ -229,7 +229,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
"c_use_crc": "false",
"c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
Expand Down Expand Up @@ -367,7 +367,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
"c_use_crc": "false",
"c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
Expand Down Expand Up @@ -505,7 +505,7 @@
"c_use_chipscope": "false",
"c_drp_if": "false",
"transceivercontrol": "false",
"c_use_crc": "false",
"c_use_crc": "true",
"supportlevel": 0,
"c_use_byteswap": "false",
"c_cpll_fbdiv": 2,
Expand Down Expand Up @@ -913,8 +913,8 @@
"m15_s15_connectivity": 1,
"component_name": "design_1_xbar_0",
"edk_iptype": "PERIPHERAL",
"c_baseaddr": 0,
"c_highaddr": 1023
"c_baseaddr": 4096,
"c_highaddr": 5119
},
"ports": [
{
Expand Down Expand Up @@ -969,7 +969,7 @@
},
{
"role": "slave",
"target": "dino_dinoif_fast_0:M00_AXIS",
"target": "dino_dinoif_adc_0:M00_AXIS",
"name": "S05_AXIS"
},
{
Expand Down Expand Up @@ -1016,32 +1016,44 @@
"vlnv": "xilinx.com:module_ref:dinoif_dac:1.0",
"i2c_channel": 1,
"parameters": {
"component_name": "design_1_dinoif_dac_0_0",
"component_name": "design_1_dinoif_adc_0_0",
"edk_iptype": "PERIPHERAL"
},
"ports": [
{
"role": "slave",
"target": "crossbar_axis_interconnect_0_xbar:M05_AXIS",
"name": "S00_AXIS"
"role": "master",
"target": "crossbar_axis_interconnect_0_xbar:S05_AXIS",
"name": "M00_AXIS"
}
]
},
"dino_dinoif_fast_0": {
"dino_dinoif_fast_nologic_0": {
"vlnv": "xilinx.com:module_ref:dinoif_fast:1.0",
"i2c_channel": 0,
"parameters": {
"component_name": "design_1_dinoif_fast_0_0",
"component_name": "design_1_dinoif_dac_0_0",
"edk_iptype": "PERIPHERAL"
},
"ports": [
{
"role": "master",
"target": "crossbar_axis_interconnect_0_xbar:S05_AXIS",
"name": "M00_AXIS"
"role": "slave",
"target": "crossbar_axis_interconnect_0_xbar:M05_AXIS",
"name": "S00_AXIS"
}
]
},
"dino_registerif_0": {
"vlnv": "xilinx.com:module_ref:registerif:1.0",
"parameters": {
"c_axi_data_width": 32,
"c_axi_addr_width": 32,
"reg_addr_width": 10,
"component_name": "design_1_registerif_0_0",
"edk_iptype": "PERIPHERAL",
"c_baseaddr": 20480,
"c_highaddr": 21503
}
},
"dma_pcie_axi_dma_0": {
"vlnv": "xilinx.com:ip:axi_dma:7.1",
"parameters": {
Expand Down Expand Up @@ -1130,6 +1142,29 @@
"s2mm_introut": "dma_pcie_pcie_pcie_interrupts_axi_pcie_intc_0:1"
}
},
"dma_pcie_axi_read_cache_0": {
"vlnv": "xilinx.com:module_ref:axi_read_cache:1.0",
"parameters": {
"c_axi_data_width": 32,
"c_axi_addr_width": 32,
"word_num": 16,
"component_name": "design_1_axi_read_cache_0_0",
"edk_iptype": "PERIPHERAL",
"c_baseaddr": 24576,
"c_highaddr": 25599
},
"memory-view": {
"M_AXI": {
"dma_pcie_pcie_axi_pcie_0": {
"BAR0": {
"baseaddr": 0,
"highaddr": 4294967295,
"size": 4294967296
}
}
}
}
},
"dma_pcie_pcie_axi_pcie_0": {
"vlnv": "xilinx.com:ip:axi_pcie:2.9",
"parameters": {
Expand Down Expand Up @@ -1158,7 +1193,7 @@
"c_interrupt_pin": 0,
"c_comp_timeout": 0,
"c_include_rc": 0,
"c_s_axi_supports_narrow_burst": 0,
"c_s_axi_supports_narrow_burst": 1,
"c_include_baroffset_reg": 1,
"c_axibar_num": 1,
"c_axibar2pciebar_0": 0,
Expand Down Expand Up @@ -1281,7 +1316,7 @@
"s_axi_data_width": 64,
"m_axi_addr_width": 32,
"m_axi_data_width": 64,
"s_axi_supports_narrow_burst": "false",
"s_axi_supports_narrow_burst": "true",
"bar_64bit": "false",
"xlnx_ref_board": "VC707",
"pcie_blk_locn": "X1Y0",
Expand Down Expand Up @@ -1332,6 +1367,20 @@
"highaddr": 17407,
"size": 1024
}
},
"dino_registerif_0": {
"reg0": {
"baseaddr": 20480,
"highaddr": 21503,
"size": 1024
}
},
"dma_pcie_axi_read_cache_0": {
"reg0": {
"baseaddr": 24576,
"highaddr": 25599,
"size": 1024
}
}
}
},
Expand Down
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