GitHub - UTehran-NavabiLab/NBGen: A tool to generate mapped netlist and bench for verilog

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A tool to generate mapped netlist and bench for verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 70 Commits
cell_library		cell_library
legacy_files		legacy_files
notes		notes
pypi_package		pypi_package
.gitignore		.gitignore
README.txt		README.txt
check_for_diff.py		check_for_diff.py

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Welcome to Netlist/Bench Generator (version 1.0)

Prof. Navabi Lab
Copyright (C) 2022, University Of Tehran

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Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED AS IS AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.