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Implement a language agnostic hardware representation
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Rhys Gretsch
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Sep 21, 2021
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| def hardwareSchema(): | ||
| ''' This function holds the schemas to check that any json hardware | ||
| representation conforms to the same requirements | ||
| All components except for inputs should have some driving logic | ||
| If the driving logic does not list an operation it is a simple | ||
| assignment operation (destination = argument) | ||
| Arguments should always be listed from left to right as one might | ||
| read them in a language like verilog | ||
| EX. a + b becomes op='+', args=[a,b] | ||
| Ex. a ? b : c becomes op='?', args=[a, b, c] | ||
| Ex. {a, b} becomes op='concat', args=[a,b] | ||
| If the module does not have a primary component (inputs, outputs, | ||
| registers, wires, memory) their field should be included with an | ||
| empty list | ||
| ''' | ||
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| nameSchema = { | ||
| "description": "The component's name", | ||
| "type": "string" | ||
| } | ||
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| bitwidthSchema = { | ||
| "description": "The number of bits this component contains", | ||
| "type": "integer" | ||
| } | ||
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| componentSchema = { | ||
| "name": nameSchema, | ||
| "bitwidth": bitwidthSchema, | ||
| "Constant value": { | ||
| "description": "If this is a constant this field holds its constant value", | ||
| "type": "integer" | ||
| }, | ||
| "driver": { | ||
| "description": "The operation or wire that drives this component", | ||
| "type": "object", | ||
| "properties": { | ||
| "op": { | ||
| "description": "Logical operation whose output is driving this component", | ||
| "type": "string" | ||
| }, | ||
| "args": { | ||
| "description": """A list of the arguments of the operation, | ||
| in order of left to right""", | ||
| "type": "array", | ||
| "items": { | ||
| "description": "Individual arguments", | ||
| "type": "string" | ||
| } | ||
| }, | ||
| "src": { | ||
| "description": "The component input into a register", | ||
| "type": "string" | ||
| }, | ||
| "rst val": { | ||
| "description": "If this is a register, this lists what it should be reset to", | ||
| "type": "integer" | ||
| } | ||
| } | ||
| } | ||
| } | ||
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| memorySchema = { | ||
| "name": nameSchema, | ||
| "bitwidth": bitwidthSchema, | ||
| "size": { | ||
| "description": "The number of addressable locations", | ||
| "type": "integer" | ||
| }, | ||
| "initial values": { | ||
| "description": "For ROM memory this outlines each address' initial value as an integer", | ||
| "type": "array", | ||
| "items": { | ||
| "description": """The index in the list is the memory address each | ||
| intial value maps to""", | ||
| "type": "integer" | ||
| } | ||
| }, | ||
| "reads": { | ||
| "description": "A list of all read operations ocurring on this memory", | ||
| "type": "array", | ||
| "items": { | ||
| "description": "A single memory read operation", | ||
| "type": "object", | ||
| "properties": { | ||
| "destination": { | ||
| "description": "The component receiving the result of the read operation", | ||
| "type": "string" | ||
| }, | ||
| "addr": { | ||
| "description": "The wire name that selects the memory address to be read", | ||
| "type": "string" | ||
| } | ||
| }, | ||
| "required": ["destination", "addr"] | ||
| } | ||
| }, | ||
| "writes": { | ||
| "description": "A list of all the write operations to this memory", | ||
| "type": "array", | ||
| "items": { | ||
| "description": "A single memory write operation", | ||
| "type": "object", | ||
| "properties": { | ||
| "addr": { | ||
| "description": """The component that selects the | ||
| memory address to be written""", | ||
| "type": "string" | ||
| }, | ||
| "data src": { | ||
| "description": """The component that provides the | ||
| data to be written to memory""", | ||
| "type": "string" | ||
| }, | ||
| "w.e": { | ||
| "description": "The component that controls the write enable if applicable", | ||
| "type": "string" | ||
| }, | ||
| }, | ||
| "required": ["addr", "data src"] | ||
| } | ||
| } | ||
| } | ||
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| exportSchema = { | ||
| # necessary for version control | ||
| "$schema": "https://json-schema.org/draft/2020-12/schema", | ||
| "title": "JSON Hardware representation", | ||
| "type": "object", | ||
| "properties": { | ||
| "module": { | ||
| "description": "The top level module", | ||
| "type": "object", | ||
| "properties": { | ||
| "name": { | ||
| "description": "The module name", | ||
| "type": "string" | ||
| }, | ||
| "inputs": { | ||
| "description": "List of inputs to the module", | ||
| "type:": "array", | ||
| "items": { | ||
| "description": "An input into the module", | ||
| "type": "object", | ||
| "properties": componentSchema, | ||
| "required": ["name", "bitwidth"] | ||
| }, | ||
| "uniqueItems": True | ||
| }, | ||
| "outputs": { | ||
| "description": "List of the module's outputs", | ||
| "type": "array", | ||
| "items": { | ||
| "description": "An output of the module", | ||
| "type": "object", | ||
| "properties": componentSchema, | ||
| "required": ["name", "bitwidth", "driver"] | ||
| }, | ||
| "uniqueItems": True | ||
| }, | ||
| "wires": { | ||
| "description": "List of the internal wires in the module", | ||
| "type": "array", | ||
| "items": { | ||
| "description": "A wire in the module", | ||
| "type": "object", | ||
| "properties": componentSchema, | ||
| "required": ["name", "bitwidth"] | ||
| }, | ||
| "uniqueItems": True | ||
| }, | ||
| "registers": { | ||
| "description": "List of the internal registers in the module", | ||
| "type": "array", | ||
| "items": { | ||
| "description": "A register in the module", | ||
| "type": "object", | ||
| "properties": componentSchema, | ||
| "required": ["name", "bitwidth", "driver"] | ||
| }, | ||
| "uniqueItems": True | ||
| }, | ||
| "memories": { | ||
| "description": "List of memories and their respective accesses", | ||
| "type": "array", | ||
| "items": { | ||
| "description": "A single memory module", | ||
| "type": "object", | ||
| "properties": memorySchema, | ||
| "required": ['name', 'bitwidth', 'size'] | ||
| }, | ||
| "uniqueItems": True | ||
| }, | ||
| }, | ||
| "required": ["name", "inputs", "outputs", | ||
| "wires", "registers", "memories"] | ||
| } | ||
| } | ||
| } | ||
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| return exportSchema |
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