Update project tt_um_vc32_cpu (MoonbaseOtago/ttihp-vc16)

projects/tt_um_vc32_cpu/commit_id.json

@@ -1,7 +1,7 @@
 {
-  "app": "Tiny Tapeout tt09 05f4c62d",
+  "app": "Tiny Tapeout tt09 b176ed7c",
   "repo": "https://github.com/MoonbaseOtago/ttihp-vc16",
-  "commit": "19954ce69f5b2839f1496ce8dabbfd24e97c0553",
-  "workflow_url": "https://github.com/MoonbaseOtago/ttihp-vc16/actions/runs/11489961942",
+  "commit": "049816098062c97bbec1768e1fd4fff4f5682c48",
+  "workflow_url": "https://github.com/MoonbaseOtago/ttihp-vc16/actions/runs/11539868371",
   "sort_id": 1729683347151
 }

projects/tt_um_vc32_cpu/stats/synthesis-stats.txt

@@ -3,59 +3,55 @@
 
 === tt_um_vc32_cpu ===
 
-   Number of wires:              17591
-   Number of wire bits:          17626
-   Number of public wires:        2507
-   Number of public wire bits:    2542
+   Number of wires:              17357
+   Number of wire bits:          17392
+   Number of public wires:        2508
+   Number of public wire bits:    2543
    Number of ports:                  8
    Number of port bits:             43
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:              15123
-     sg13g2_a21o_1                 151
-     sg13g2_a21oi_1                880
-     sg13g2_a21oi_2                 12
-     sg13g2_a221oi_1               242
-     sg13g2_a22oi_1                693
-     sg13g2_and2_1                 229
-     sg13g2_and3_1                  42
-     sg13g2_and3_2                   6
-     sg13g2_and4_1                  44
-     sg13g2_buf_1                 1608
+   Number of cells:              14888
+     sg13g2_a21o_1                 121
+     sg13g2_a21oi_1                871
+     sg13g2_a21oi_2                  4
+     sg13g2_a221oi_1               211
+     sg13g2_a22oi_1                768
+     sg13g2_and2_1                 220
+     sg13g2_and3_1                  37
+     sg13g2_and4_1                  57
+     sg13g2_buf_1                 1716
      sg13g2_buf_16                   2
-     sg13g2_buf_2                  295
-     sg13g2_buf_4                   97
-     sg13g2_buf_8                   85
-     sg13g2_dfrbp_1               2484
-     sg13g2_inv_1                  325
-     sg13g2_inv_2                    6
-     sg13g2_inv_4                    3
-     sg13g2_mux2_1                1749
-     sg13g2_mux2_2                   1
-     sg13g2_mux4_1                 313
-     sg13g2_nand2_1               1576
-     sg13g2_nand2_2                  2
-     sg13g2_nand2b_1               216
-     sg13g2_nand3_1                377
-     sg13g2_nand3b_1                49
-     sg13g2_nand4_1                192
-     sg13g2_nor2_1                 868
-     sg13g2_nor2_2                  10
-     sg13g2_nor2b_1                351
-     sg13g2_nor2b_2                  3
-     sg13g2_nor3_1                 260
-     sg13g2_nor3_2                  15
-     sg13g2_nor4_1                  96
-     sg13g2_nor4_2                   7
-     sg13g2_o21ai_1               1467
-     sg13g2_or2_1                   88
+     sg13g2_buf_2                  240
+     sg13g2_buf_4                  112
+     sg13g2_buf_8                   40
+     sg13g2_dfrbp_1               2485
+     sg13g2_inv_1                  272
+     sg13g2_inv_2                    7
+     sg13g2_mux2_1                1918
+     sg13g2_mux4_1                 302
+     sg13g2_nand2_1               1362
+     sg13g2_nand2_2                  1
+     sg13g2_nand2b_1               247
+     sg13g2_nand3_1                348
+     sg13g2_nand3b_1                56
+     sg13g2_nand4_1                171
+     sg13g2_nor2_1                 932
+     sg13g2_nor2_2                   3
+     sg13g2_nor2b_1                333
+     sg13g2_nor3_1                 247
+     sg13g2_nor3_2                   3
+     sg13g2_nor4_1                  91
+     sg13g2_nor4_2                  11
+     sg13g2_o21ai_1               1320
+     sg13g2_or2_1                  102
      sg13g2_or3_1                   27
-     sg13g2_or4_1                   26
+     sg13g2_or4_1                   27
      sg13g2_tiehi                    1
-     sg13g2_xnor2_1                166
-     sg13g2_xor2_1                  59
+     sg13g2_xnor2_1                156
+     sg13g2_xor2_1                  67
 
-   Chip area for module '\tt_um_vc32_cpu': 256072.735800
-     of which used for sequential elements: 117181.209600 (45.76%)
+   Chip area for module '\tt_um_vc32_cpu': 254625.638400
+     of which used for sequential elements: 117228.384000 (46.04%)
 

projects/tt_um_vc32_cpu/tool_versions.json

@@ -3,5 +3,5 @@
   "openroad": "v2.0-16649-g40811f37f",
   "klayout": "KLayout 0.29.7",
   "orfs": "980de246ed15fde469d98bd2d88084b9559ea7f2",
-  "ihp_pdk": "ff292fcd5d1f1d54c68078ce23853058ce3c95cc"
+  "ihp_pdk": "a30fb07ff99c88126a66a44bd1fe3be238705642"
 }