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Update project tt_um_urish_sram_test (urish/ttihp-sram-test) #134

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merged 1 commit into from
Nov 4, 2024
Merged

Update project tt_um_urish_sram_test (urish/ttihp-sram-test) #134

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6 changes: 3 additions & 3 deletions projects/tt_um_urish_sram_test/commit_id.json
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
{
"app": "Tiny Tapeout tt09 b176ed7c",
"app": "Tiny Tapeout ttihp0p2-skip-lvs 209c754a",
"repo": "https://github.com/urish/ttihp-sram-test",
"commit": "32715de6d322bbfbdc191584879b1a4f937e929d",
"workflow_url": "https://github.com/urish/ttihp-sram-test/actions/runs/11666708894",
"commit": "2632a9900f668e66340abd46a1452736d07a29c1",
"workflow_url": "https://github.com/urish/ttihp-sram-test/actions/runs/11672208655",
"sort_id": 1730732717591
}
310 changes: 161 additions & 149 deletions projects/tt_um_urish_sram_test/stats/metrics.csv
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25 changes: 16 additions & 9 deletions projects/tt_um_urish_sram_test/stats/synthesis-stats.txt
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Original file line number Diff line number Diff line change
@@ -1,21 +1,28 @@

17. Printing statistics.
18. Printing statistics.

=== tt_um_urish_sram_test ===

Number of wires: 9
Number of wire bits: 44
Number of public wires: 8
Number of public wire bits: 43
Number of wires: 28
Number of wire bits: 63
Number of public wires: 16
Number of public wire bits: 51
Number of ports: 8
Number of port bits: 43
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 25
sg13g2_buf_1 24
Number of cells: 33
RM_IHPSG13_1P_1024x8_c2_bm_bist 1
sg13g2_and2_1 4
sg13g2_buf_1 16
sg13g2_dfrbp_1 4
sg13g2_inv_1 1
sg13g2_mux2_1 4
sg13g2_nor2_1 1
sg13g2_tiehi 1
sg13g2_tielo 1

Chip area for module '\tt_um_urish_sram_test': 181.440000
of which used for sequential elements: 0.000000 (0.00%)
Chip area for module '\tt_um_urish_sram_test': 49860.144000
of which used for sequential elements: 188.697600 (0.38%)

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62 changes: 52 additions & 10 deletions projects/tt_um_urish_sram_test/tt_um_urish_sram_test.lef
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Expand Up @@ -41,6 +41,15 @@ VIA tt_um_urish_sram_test_via4_5_2200_440_1_5_410_410
ROWCOL 1 5 ;
END tt_um_urish_sram_test_via4_5_2200_440_1_5_410_410

VIA tt_um_urish_sram_test_via4_5_2200_2810_6_4_480_480
VIARULE via4Array ;
CUTSIZE 0.19 0.19 ;
LAYERS Metal4 Via4 Metal5 ;
CUTSPACING 0.29 0.29 ;
ENCLOSURE 0.285 0.11 0.285 0.05 ;
ROWCOL 6 4 ;
END tt_um_urish_sram_test_via4_5_2200_2810_6_4_480_480

MACRO tt_um_urish_sram_test
FOREIGN tt_um_urish_sram_test 0 0 ;
CLASS BLOCK ;
Expand Down Expand Up @@ -394,11 +403,27 @@ MACRO tt_um_urish_sram_test
USE GROUND ;
PORT
LAYER Metal5 ;
RECT 412.28 3.56 414.48 310.18 ;
RECT 393.38 3.56 395.58 310.18 ;
RECT 374.48 3.56 376.68 310.18 ;
RECT 355.58 3.56 357.78 310.18 ;
RECT 336.68 3.56 338.88 310.18 ;
RECT 317.78 3.56 319.98 310.18 ;
RECT 298.88 3.56 301.08 310.18 ;
RECT 279.98 3.56 282.18 310.18 ;
RECT 261.08 3.56 263.28 310.18 ;
RECT 242.18 3.56 244.38 310.18 ;
RECT 223.28 3.56 225.48 310.18 ;
RECT 204.38 3.56 206.58 310.18 ;
RECT 185.48 3.56 187.68 310.18 ;
RECT 166.58 3.56 168.78 310.18 ;
RECT 147.68 3.56 149.88 310.18 ;
RECT 128.78 3.56 130.98 310.18 ;
RECT 109.88 3.56 112.08 310.18 ;
RECT 90.98 3.56 93.18 310.18 ;
RECT 72.08 3.56 74.28 310.18 ;
RECT 53.18 3.56 55.38 310.18 ;
RECT 34.28 3.56 36.48 310.18 ;
RECT 15.38 3.56 17.58 310.18 ;
END
END VGND
Expand All @@ -407,24 +432,41 @@ MACRO tt_um_urish_sram_test
USE POWER ;
PORT
LAYER Metal5 ;
RECT 355.58 3.56 357.78 310.18 ;
RECT 279.98 3.56 282.18 310.18 ;
RECT 204.38 3.56 206.58 310.18 ;
RECT 128.78 3.56 130.98 310.18 ;
RECT 53.18 3.56 55.38 310.18 ;
RECT 421.73 3.56 423.93 310.18 ;
RECT 402.83 3.56 405.03 310.18 ;
RECT 383.93 3.56 386.13 310.18 ;
RECT 365.03 3.56 367.23 310.18 ;
RECT 346.13 3.56 348.33 310.18 ;
RECT 327.23 3.56 329.43 310.18 ;
RECT 308.33 3.56 310.53 310.18 ;
RECT 289.43 3.56 291.63 310.18 ;
RECT 270.53 3.56 272.73 310.18 ;
RECT 251.63 3.56 253.83 310.18 ;
RECT 232.73 3.56 234.93 310.18 ;
RECT 213.83 3.56 216.03 310.18 ;
RECT 194.93 3.56 197.13 310.18 ;
RECT 176.03 3.56 178.23 310.18 ;
RECT 157.13 3.56 159.33 310.18 ;
RECT 138.23 3.56 140.43 310.18 ;
RECT 119.33 3.56 121.53 310.18 ;
RECT 100.43 3.56 102.63 310.18 ;
RECT 81.53 3.56 83.73 310.18 ;
RECT 62.63 3.56 64.83 310.18 ;
RECT 43.73 3.56 45.93 310.18 ;
RECT 24.83 3.56 27.03 310.18 ;
END
END VPWR
OBS
LAYER Metal1 ;
RECT 2.88 3.56 424.32 313.74 ;
RECT 2.605 3.56 424.32 313.74 ;
LAYER Metal2 ;
RECT 2.88 3.56 424.32 313.74 ;
RECT 2.605 3.56 424.32 313.74 ;
LAYER Metal3 ;
RECT 2.88 3.56 424.32 313.74 ;
RECT 2.605 3.56 424.32 313.74 ;
LAYER Metal4 ;
RECT 2.88 3.56 424.32 313.74 ;
RECT 2.605 3.56 424.32 313.74 ;
LAYER Metal5 ;
RECT 2.88 3.56 424.32 313.74 ;
RECT 2.605 3.56 424.32 313.74 ;
END
END tt_um_urish_sram_test
END LIBRARY
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