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feat: update project tt_um_MichaelBell_latch_mem from MichaelBell/tt0…
…6-memory Commit: 9ba7c7d578af66f720422faec75cd3a53f291473 Workflow: https://github.com/MichaelBell/tt06-memory/actions/runs/8758769642
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY | ||
/work/src,tt_um_MichaelBell_latch_mem,wokwi,flow completed,0h5m45s0ms,0h5m16s0ms,146034.02336544375,0.01795472,73017.01168272187,87.38,88.3629,601.02,1210,0,0,0,0,0,0,0,1,1,0,-1,-1,50580,11145,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,25104298.0,0.0,78.19,73.12,49.47,30.96,-1,1266,1808,223,765,0,0,0,1782,18,1,7,15,494,0,0,32,550,119,8,247,225,9,380,1311,2172,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.88,0,sky130_fd_sc_hd,AREA 0 | ||
/work/src,tt_um_MichaelBell_latch_mem,wokwi,flow completed,0h5m44s0ms,0h5m16s0ms,146034.02336544375,0.01795472,73017.01168272187,87.38,88.3629,601.38,1210,0,0,0,0,0,0,0,1,1,0,-1,-1,50580,11145,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,25104298.0,0.0,78.19,73.12,49.47,30.96,-1,1266,1808,223,765,0,0,0,1782,18,1,7,15,494,0,0,32,550,119,8,247,225,9,380,1311,2172,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.88,0,sky130_fd_sc_hd,AREA 0 |
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projects/tt_um_MichaelBell_latch_mem/tt_um_MichaelBell_latch_mem.gds
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projects/tt_um_MichaelBell_latch_mem/tt_um_MichaelBell_latch_mem.spef
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