feat: update project tt_um_vks_pll from engrvip123/tt_um_vks_pll

Commit: b916f044b6d3b768ef335d7fe6bce585c5c9981d
Workflow: https://github.com/engrvip123/tt_um_vks_pll/actions/runs/8739246638

projects/tt_um_vks_pll/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "custom_gds action",
   "repo": "https://github.com/engrvip123/tt_um_vks_pll",
-  "commit": "dca30943876d9de2c0338cc6a736a95329acd673",
-  "workflow_url": "https://github.com/engrvip123/tt_um_vks_pll/actions/runs/8642470160",
+  "commit": "b916f044b6d3b768ef335d7fe6bce585c5c9981d",
+  "workflow_url": "https://github.com/engrvip123/tt_um_vks_pll/actions/runs/8739246638",
   "sort_id": 1712734771241,
   "analog": true
 }

projects/tt_um_vks_pll/docs/info.md

@@ -9,12 +9,41 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-A PFD circuit is a phase frequency detector circuit, which is used to measure the phase and frequency difference between two input signals. A PFD circuit is often a part of a phase-locked loop (PLL), which is a feedback system that synchronizes the output signal of a voltage-controlled oscillator (VCO) with a reference signal. A PFD circuit can be implemented using different logic gates, such as NAND, NOR, or AND gates. A common PFD circuit consists of two edge-triggered D flip-flops and a NAND gate in the reset path.
+This design contains individual blocks used to realize a PLL circuit. These blocks are designed by participants under SSP (Saudi Semicondcutor Program) using open-source analog EDA tools. There are 4 blocks designed by multiple individuals and teams: 
+
+**Phase Frequency Detector (PFD)**: D flip-flop-based phase frequency detector (PFD) with inputs A and B, and outputs QA and QB compares the phases of two input signals, A and B, and generates output pulses to indicate the phase difference between them. When A leads B, the output QA transitions high, while QB transitions low. Conversely, when B leads A, QA transitions low and QB transitions high. If both signals are in phase, neither QA nor QB transitions. PFD's output signals can be used to control the frequency and phase of a voltage-controlled oscillator (VCO) in a PLL system, thereby locking the output frequency and phase to the reference input. This is essential in applications such as clock synchronization, frequency synthesis, and communication systems, ensuring precise timing and synchronization. ![Phase Frequency Detector](pfd.png "Phase Frequency Detector")
+
+**Charge Pump (CP)**: Charge pump circuit converts the output signals from the PFD into a control voltage for Voltage-Controlled Oscillator(VCO). Charge pump circuit consists of a pair of switches and a capacitor. When the PFD generates a positive pulse, one switch connects the capacitor to a reference voltage, charging it. Conversely, when the PFD generates a negative pulse, the other switch connects the capacitor to ground, discharging it. This creates a control voltage proportional to the phase difference between the input and reference signals. ![Charge Pump ](cp.png "Charge Pump")
+
+**Voltage Controlled Oscillator(VCO)**: A ring oscillator Voltage-Controlled Oscillator (VCO) consists of odd number of inverting stages connected in a ring configuration, generating an oscillating waveform. By controlling the bias voltage of the transistors within the stages, the oscillation frequency can be adjusted. This VCO serves as the controlled oscillator in the PLL, with its frequency locked to the reference signal through the feedback loop.  ![VCO ](vco.png "VCO")
+
+**Frequency Divider(FD)**: A D flip-flop frequency divider divides the frequency of VCO output signal by a fixed integer ratio. This division process creates a feedback mechanism that compares the divided output frequency with the reference frequency. The D flip-flop's toggling action divides the frequency by 2/4/8, allowing for frequency multiplication or division within PLL loop. ![Frequency Divider](fd.png "Frequency Divider")
+
+
+| | Designer Name           | Block Name               |
+|-| ------------------------| ------------------------ |
+|1| Abdulrahman Alghamdi    | Frequency Divider (FD-1) |
+|2| Abdulrahman Alghamdi 	| PFD (PFD-1)              |
+|3| Baraa Musa Abdullah 	| PFD (PFD-2)              |
+|4| Faisal Tareq 		| Charge Pump (CP-1)       |
+|5| Khalid Abdulaziz 	| Frequency Divider (FD-2) |
+|6| Khowla Alkhulayfi       | Frequency Divider (FD-3) |
+|7| Nawaf                   | VCO                      |
+|8| Nawaf			| Frequency Divider (FD-4) |
+
 
 ## How to test
 
-This section will be updated later on
+**PFD**: Apply input pulses with phase difference between them and A and B pins at PFD input. Observe the output at QA and QB pins with output pulses based on +ve or -ve phase difference between signal applied at input pins of PFD.
+
+**CP**: Apply input pulses at QA and QB input pins of charge pump replicating the output of PFD circuit. Based on whether QA or QB pulses are high, the output of charge pump circuit will demonstrate charging and discharging behaviour respectively. Charging and discharging rate can be controlled by changing bias voltage cp_bias to either increase of decrease current.
+
+**VCO**: Apply a control voltage, vctrl=0.9V to VCO's input and measure the resulting output frequency. Verify that the output frequency varies with the applied control voltage within the specified range i.e. 0.75V to 1V. Check VCO frequency tuning range by sweeping the control voltage across and observing the output frequency response.
+
+**FD**: Input a signal with a frequency (40 to 80MHz range) to input of frequency divider. Measure the output frequency using a oscilloscope. Verify that the output frequency is one-eighth of the input frequency.
+
 
 ## External hardware
+2-channel function/waveform generator with varying frequency and pulse time generation.
+2-channel Oscilloscope to measure output signal waveforms.
 
-Requires function generator and oscilloscope for measurements. No other h/w required.

projects/tt_um_vks_pll/info.yaml

@@ -1,9 +1,9 @@
 # Tiny Tapeout project information
 project:
-  title:        "PLL"      # Project title
-  author:       "vks"      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "PLL"      # One line description of what your project does
+  title:        "PLL blocks"      # Project title
+  author:       "Vipul Sharma"      # Your name
+  discord:      "vks"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "This design contains blocks used in PLL circuit"      # One line description of what your project does
   language:     "Analog" # other examples include Verilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
@@ -20,34 +20,34 @@ project:
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "QA"
-  ui[1]: "QB"
-  ui[2]: "Clk"
-  ui[3]: "fo"
+  ui[0]: "CP-1:QA"
+  ui[1]: "CP-1:QB"
+  ui[2]: "FD-2:Clk"
+  ui[3]: "FD-3:fo"
   ui[4]: ""
   ui[5]: ""
   ui[6]: ""
   ui[7]: ""
 
   # Outputs
-  uo[0]: "QA"
-  uo[1]: "QB"
-  uo[2]: "fo_4"
-  uo[3]: "fo_8"
-  uo[4]: "fo_4"
-  uo[5]: "fo_8"
-  uo[6]: "Out_4"
-  uo[7]: "Out_8"
+  uo[0]: "PFD-2:QA"
+  uo[1]: "PFD-2:QB"
+  uo[2]: "FD-2:fo_4"
+  uo[3]: "FD-2:fo_8"
+  uo[4]: "FD-3:fo_4"
+  uo[5]: "FD-3:fo_8"
+  uo[6]: "FD-4:Out_4"
+  uo[7]: "FD-4:Out_8"
 
   # Bidirectional pins
-  uio[0]: "fo"
-  uio[1]: "fo_by_8"
-  uio[2]: "A"
-  uio[3]: "B"
-  uio[4]: "QA"
-  uio[5]: "QB"
-  uio[6]: "A"
-  uio[7]: "B"
+  uio[0]: "FD-1:fo"
+  uio[1]: "FD-1:fo_by_8"
+  uio[2]: "PFD-1:A"
+  uio[3]: "PFD-1:B"
+  uio[4]: "PFD-1:QA"
+  uio[5]: "PFD-1:QB"
+  uio[6]: "PFD-2:A"
+  uio[7]: "PFD-2:B"
 
   # Analog pins - you can add more if you use them, up to 8
   ua[0]: "CP_bias"