feat: update project tt_um_jv_sigdel from JVollrath/tt06_jv_sigdel_v

Commit: 6725319ea7d73496fad411689efb281ca0485f81
Workflow: https://github.com/JVollrath/tt06_jv_sigdel_v/actions/runs/8537922080

projects/tt_um_jv_sigdel/commit_id.json

@@ -1,9 +1,9 @@
 {
-  "app": "Tiny Tapeout tt06 e3fac0ab",
+  "app": "Tiny Tapeout tt06 b544d27d",
   "repo": "https://github.com/JVollrath/tt06_jv_sigdel_v",
-  "commit": "d609c4fb20c9691705a088ad9dde067fd171415a",
-  "workflow_url": "https://github.com/JVollrath/tt06_jv_sigdel_v/actions/runs/8395755848",
+  "commit": "6725319ea7d73496fad411689efb281ca0485f81",
+  "workflow_url": "https://github.com/JVollrath/tt06_jv_sigdel_v/actions/runs/8537922080",
   "sort_id": 1710957554982,
-  "openlane_version": "OpenLane f691c8c0712ca6c6645e3fd548985b3cbcf08c78",
-  "pdk_version": "open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571"
+  "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
+  "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
 }

projects/tt_um_jv_sigdel/docs/info.md

@@ -25,6 +25,91 @@ Select sampling, oversamplingrate and filter in1..6.
 The 4 output lines 0..3 should give a 4-Bit value.
 The out6,7 give a pwm signal changing with the input voltage.
 
-## External hardware
+All subcircuits were tested in one testfile tb_sigdel do be able to observe all signals.
+
+![Figure: Circuit simulation](TTsigdelSim.jpg "Circuit simulation")
+
+
+## BASYS3 board measurements
+
+22k resistors were used with 100 and 560 pF capacitances.
+
+The signals at the capacitor and the digital signal inx were measured 
+with an Electronic Explorer board.
+
+Measurement showed a missing enable signal for inx sampling.
+
+The table shows valid configuration options.
+
+inp[6] 	inp[5] 	inp[4] 	inp[3] 	inp[2] 	inp[1] 	Cint 	fCLK=50MHz 	T=20ns 	OSR 	Ldmax 	Bits
+
+0 	1 	0 	0 	0 	0 	100pF 	SINC1 fsCLK 	40ns 	256 	LD7 	8
+
+0 	1 	0 	0 	0 	1 	        SINC1 fsCLK 	160ns 	64 	      6
+
+0 	1 	0 	1 	0 	0 	100 pF 	SINC1 fsCLK 	40ns 	1024 	LD9 	10
+
+0 	1 	0 	1 	0 	1 	      	SINC1 fsCLK 	160ns 	256 	8
+
+0 	1 	0 	1 	1 	0 	      	SINC1 fsCLK 	640ns 	64 	  6
+
+0 	1 	1 	0 	0 	0 	       	SINC1 fsCLK 	40ns 	4096 	12
+
+0 	1 	1 	0 	0 	1 		SINC1 fsCLK 	160ns 	1024 	10
+
+0 	1 	1 	0 	1 	0 	560 pF 	SINC1 fsCLK 	640ns 	256 		8	ok
+
+0 	1 	1 	0 	1 	1 	560pF 	SINC1 fsCLK 	2560ns 	64 	LD5 	6	ok
+
+0 	1 	1 	1 	0 	0 		SINC1 fsCLK 	40ns 	16384 		14	
+
+0 	1 	1 	1 	0 	1 	560 pF 	SINC1 fsCLK 	160ns 	4096 		12	ok
+
+0 	1 	1 	1 	1 	0 	560 pF 	SINC1 fsCLK 	640ns 	1024 	10	ok
+
+0 	1 	1 	1 	1 	1 	560 pF 	SINC1 fsCLK 	2560ns 	256 		8	ok
+
+1 	0 	0 	0 	0 	1 	      	SINC2 fsCLK           	64  12
+
+1 	0 	0 	0 	1 	0 	      	SINC2 fsCLK 	        16	8
+
+1 	0 	0 	1 	1 	0 	      	SINC2 fsCLK         	64	12
+
+1 	0 	0 	1 	1 	1 	560pF 	SINC2 fsCLK 		16 	LD7 	8
+
+1 	0 	1 	0 	1 	1 	560 pF 	SINC2 fsCLK 		64 	LD11 	12
+
+1 	1 	0 	0 	1 	0 		      SINC3 fsCLK 	16 	12
+
+1 	1 	0 	0 	1 	1 	560 pF 	SINC3 fsCLK 		4 	LD5 	6
+
+1 	1 	0 	1 	1 	1 	560 pF 	SINC3 fsCLK 		16 	LD11 	12
+
+A better configuration scheme should be chosen in the next design.<br>
+Higher fsCLK have lower capacitance.
+
+A better multiplexing to the 4 Bit output with a case statement was done at the FPGA
+and the routing of out[3:0] done to led[3:0].
+
+![Oscilloscope picture BASYS3](TTsigdelOsci.jpg "Oscilloscope picture BASYS3")
+
+Figure: Oscilloscope picture BASYS3 FPGA not(inx)(blue) and inp[0](orange)
+
+
+## Summary
+
+It is possible with this circuit to look at the influence of R, C and 
+oversampling on the accuracy of a 1st order sigma delta ADC.
+
+Bad R,C values can cause non linearities or signal limitation to VDD and ground.
+
+The order of the SINC filter can lead to less resolution (SNR) than expected.
+
+The order of the SINC filter should be at least one more than the sigma delta modulator.
+
+The pwm signal has 10 bits and can be used for more precise output values.
+
+## References
+Martin Knauer, Jörg Vollrath, 'Implementation and Testing of a FPGA Based Sigma Delta Analog to Digital Converter', 
+[58. MPC Workshop, Reutlingen July 2017](https://www.mpc-gruppe.de/workshopbaende)
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any

projects/tt_um_jv_sigdel/info.yaml

@@ -15,6 +15,8 @@ project:
 
   # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
   source_files:        
+    - "modNCnt.v"
+    - "serTXa.v"
     - "sinc1.v"
     - "sinc2.v"
     - "sinc3.v"

projects/tt_um_jv_sigdel/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_jv_sigdel,wokwi,flow completed,0h4m11s0ms,0h3m15s0ms,73066.35834815048,0.0756025088,36533.17917407524,35.83,81.71770000000001,609.62,2435,0,0,0,0,0,0,0,4,4,0,-1,-1,66508,17965,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,41591414.0,0.0,33.79,21.56,6.11,0.94,-1,1623,2439,96,846,0,0,0,2155,84,0,80,261,173,367,120,58,392,388,21,3762,1037,8,1424,2762,8993,72564.5952,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,153.18,153.6,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_jv_sigdel,wokwi,flow completed,0h4m8s0ms,0h3m13s0ms,75817.58979934803,0.0756025088,37908.794899674016,35.85,40.7028,623.61,2433,0,0,0,0,0,0,0,0,0,0,-1,-1,65373,18559,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,41831015.0,0.0,34.46,20.93,4.99,0.91,-1,1624,2447,97,854,0,0,0,2155,84,0,80,261,173,367,120,58,392,388,21,3701,1037,3,1390,2866,8997,72564.5952,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,153.18,153.6,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_jv_sigdel/stats/synthesis-stats.txt

@@ -1,68 +1,64 @@
 
-68. Printing statistics.
+71. Printing statistics.
 
 === tt_um_jv_sigdel ===
 
-   Number of wires:               2419
-   Number of wire bits:           2454
+   Number of wires:               2417
+   Number of wire bits:           2452
    Number of public wires:         391
    Number of public wire bits:     426
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:               2435
-     sky130_fd_sc_hd__a2111o_2       1
-     sky130_fd_sc_hd__a211o_2        9
+   Number of cells:               2433
+     sky130_fd_sc_hd__a211o_2       10
      sky130_fd_sc_hd__a211oi_2       5
      sky130_fd_sc_hd__a21bo_2        6
      sky130_fd_sc_hd__a21boi_2       6
-     sky130_fd_sc_hd__a21o_2        68
+     sky130_fd_sc_hd__a21o_2        70
      sky130_fd_sc_hd__a21oi_2       94
      sky130_fd_sc_hd__a221o_2        7
-     sky130_fd_sc_hd__a22o_2         4
+     sky130_fd_sc_hd__a22o_2         5
      sky130_fd_sc_hd__a2bb2o_2       2
-     sky130_fd_sc_hd__a311o_2        2
-     sky130_fd_sc_hd__a31o_2        45
+     sky130_fd_sc_hd__a311o_2        3
+     sky130_fd_sc_hd__a31o_2        42
      sky130_fd_sc_hd__a31oi_2        4
-     sky130_fd_sc_hd__a32o_2         4
-     sky130_fd_sc_hd__and2_2        67
-     sky130_fd_sc_hd__and2b_2       78
-     sky130_fd_sc_hd__and3_2        64
-     sky130_fd_sc_hd__and3b_2       35
-     sky130_fd_sc_hd__and4_2         1
-     sky130_fd_sc_hd__and4bb_2       1
+     sky130_fd_sc_hd__a32o_2         5
+     sky130_fd_sc_hd__and2_2        68
+     sky130_fd_sc_hd__and2b_2       79
+     sky130_fd_sc_hd__and3_2        62
+     sky130_fd_sc_hd__and3b_2       36
      sky130_fd_sc_hd__buf_1        146
-     sky130_fd_sc_hd__buf_2          3
-     sky130_fd_sc_hd__conb_1        16
+     sky130_fd_sc_hd__buf_2         11
+     sky130_fd_sc_hd__conb_1         8
      sky130_fd_sc_hd__dfxtp_2      383
-     sky130_fd_sc_hd__inv_2         41
+     sky130_fd_sc_hd__inv_2         38
      sky130_fd_sc_hd__mux2_2         7
      sky130_fd_sc_hd__mux4_2         3
-     sky130_fd_sc_hd__nand2_2      219
-     sky130_fd_sc_hd__nand3_2        2
-     sky130_fd_sc_hd__nor2_2       183
+     sky130_fd_sc_hd__nand2_2      218
+     sky130_fd_sc_hd__nand3_2        4
+     sky130_fd_sc_hd__nor2_2       186
      sky130_fd_sc_hd__nor2b_2        2
-     sky130_fd_sc_hd__nor3_2         3
-     sky130_fd_sc_hd__o2111a_2       1
+     sky130_fd_sc_hd__nor3_2         4
      sky130_fd_sc_hd__o211a_2      258
-     sky130_fd_sc_hd__o21a_2        34
-     sky130_fd_sc_hd__o21ai_2      127
+     sky130_fd_sc_hd__o21a_2        38
+     sky130_fd_sc_hd__o21ai_2      124
      sky130_fd_sc_hd__o21ba_2        1
-     sky130_fd_sc_hd__o21bai_2       6
-     sky130_fd_sc_hd__o221a_2       17
-     sky130_fd_sc_hd__o22a_2         7
-     sky130_fd_sc_hd__o2bb2a_2       4
-     sky130_fd_sc_hd__o311a_2        3
-     sky130_fd_sc_hd__o31a_2         7
-     sky130_fd_sc_hd__o32a_2        10
-     sky130_fd_sc_hd__or2_2        201
-     sky130_fd_sc_hd__or2b_2        58
-     sky130_fd_sc_hd__or3_2         18
-     sky130_fd_sc_hd__or3b_2         4
+     sky130_fd_sc_hd__o21bai_2       5
+     sky130_fd_sc_hd__o221a_2       16
+     sky130_fd_sc_hd__o22a_2         8
+     sky130_fd_sc_hd__o2bb2a_2       5
+     sky130_fd_sc_hd__o311a_2        4
+     sky130_fd_sc_hd__o31a_2         6
+     sky130_fd_sc_hd__o32a_2         9
+     sky130_fd_sc_hd__or2_2        196
+     sky130_fd_sc_hd__or2b_2        59
+     sky130_fd_sc_hd__or3_2         20
+     sky130_fd_sc_hd__or3b_2         2
      sky130_fd_sc_hd__or4_2          1
      sky130_fd_sc_hd__or4b_2         1
-     sky130_fd_sc_hd__xnor2_2      111
-     sky130_fd_sc_hd__xor2_2        55
+     sky130_fd_sc_hd__xnor2_2      108
+     sky130_fd_sc_hd__xor2_2        58
 
-   Chip area for module '\tt_um_jv_sigdel': 25316.780800
+   Chip area for module '\tt_um_jv_sigdel': 25328.041600