feat: update project tt_um_ejfogleman_smsdac from ejfogleman/ef_smsdac

Commit: 65fd05492cf31a53f0d17d11e8dfa3052d8aa094
Workflow: https://github.com/ejfogleman/ef_smsdac/actions/runs/8745545111

projects/tt_um_ejfogleman_smsdac/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt06 c74b14ac",
   "repo": "https://github.com/ejfogleman/ef_smsdac",
-  "commit": "8ad0831be891e70cbb849361effa274c952b82f3",
-  "workflow_url": "https://github.com/ejfogleman/ef_smsdac/actions/runs/8743080092",
+  "commit": "65fd05492cf31a53f0d17d11e8dfa3052d8aa094",
+  "workflow_url": "https://github.com/ejfogleman/ef_smsdac/actions/runs/8745545111",
   "sort_id": 1713416365011,
   "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_ejfogleman_smsdac/docs/info.md

@@ -9,17 +9,32 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## Operation
 
-This design implements a linear 8-bit DAC suitable for low-frequency inputs.  An analog voltage is produced by connecting the encoder's outputs to a modified R-2R ladder on the PCB.  The modification converts it into an R-(4R-4R) ladder.  It achieves high-linearity by using segmented mismatch-shaping, so the DAC does not require matched resistors.  Error due to resistor mismatch appears at the output as 1st-order highpass shaped noise.  The encoder also reduces the bit-width from 8-bits, and quantization error is also 1st-order highpass shaped.  Thus, with passive filtering, a linear, low-noise dc output can be achieved.
+This design implements a linear 8-bit DAC suitable for dc and low-frequency inputs.  An analog voltage is produced by connecting the encoder's outputs to a modified R-2R ladder on the PCB (see External Hardware).  It achieves high-linearity by using segmented mismatch-shaping, so the DAC does not require matched resistors.  The encoder provides 1st order mismatch and quantization noise shaping.  With a clock frequency of 6.144 MHz and a lowpass filter corner of 24 kHz, the oversampling ratio (OSR) is 256.
+
+Error due to resistor mismatch appears at the output as 1st-order highpass shaped noise.  The encoder also reduces the bit-width from 8-bits, and quantization error is also 1st-order highpass shaped.  Thus, with passive filtering, a linear, low-noise dc output can be achieved.  The theory behind this encoder is described in: [A. Fishov, E. Fogleman, E. Siragusa, I. Galton, "Segmented Mismatch-Shaping D/A Conversion", IEEE International Symposium on Circuits and Systems (ISCAS), 2002](https://https://ieeexplore.ieee.org/document/1010547/)
 
 Ideally, this encoder would be buffered through a clean analog supply and retimed to reduce glitches on output transitions.  However, reasonable performance should be possible driving the resistor ladder directly from the encoder through the IO supply.  
 
 ## How to test
 
-Digital testing is possible by applying clock (1-50 MHz), a static data input on ui[7:0], and summing the output on uo[7:0] with the following weights: 
-d_out = 8*uo[7:6] + 4*uo[5:4] + 2*uo[3:2] + uo[1:0]
+DAC input data is provided through `ui_in[7:0]`, and the encoder uses the project clock for mismatch shaping.  Clock frequencies in the range of 1-10 MHz are reasonable.  Higher clock frequency increases the OSR but may increase glitch error.  The encoder output is `uo_out[7:0]`, and it can be reconstructed by summing the bits with the following weights: 
+
+    out = 8*uo_out[7]+uo_out[6]) + 4*(uo_out[5]+uo_out[4]) + 2*uo_out[3]+uo_out[2]) + uo_out[1]+uo_out[0]
+
+The resistor ladder shown below sums the outputs with this weighting.  Any output network that can create this weighting will work.  
 
-The DAC is free-running off the project clock, and inputs appear at the output immediately after passing through a pair of clock sync registers.
+The DAC is free-running off the project clock, and inputs appear at the output immediately after passing through a pair of clock sync registers.  A simple dc test can be performed using the input DIP switches and the resistor ladder.  It is possible to input dynamic waveforms from the microcontroller as well. 
+
+The encoder has four modes of operation determined by `uio_in[1:0]`:
+* 3:  1st order mismatch-shaping with dither
+* 2:  randomization (flat spectral shaping)
+* 1:  1st order shaping, no dither
+* 0:  static encoding (no linearization)
 
 ## External hardware
 
-An external resistor ladder is required to create the analog output voltage, and a capacitor is required to filter high-frequency noise.  
+Technically, this is a mismatch shaping DAC encoder.  For a high-performance DAC, it is best to use a precision reference voltage and a clean clock source for edge retiming.  However, it is possible to connect the encoder directly to a resistor ladder.  In this case, the digital IO supply acts as the DAC's reference voltage, and timing skews between the `uo_out` bits may impact performance.  
+
+An external resistor ladder is required to create the analog output voltage, and a capacitor is required to filter high-frequency noise.  The termination resistors are placed at the ends of the ladder to ensure that each section has nominally identical load resistance.  
+
+The suggested unit R value is 10 kOhm.  The equivalent output resistance of the network at __v_out__ is 10 kOhm.  A 680 pF output capacitor provides a 23 kHz lowpass corner.  With this choice of R, the minimum load resistance on each `uo_out` pin is 60 kOhm, and the driver will source a maximum of 55 uA at 3.3 V.

projects/tt_um_ejfogleman_smsdac/info.yaml

@@ -1,6 +1,6 @@
 # Tiny Tapeout project information
 project:
-  title:        "ef_smsdac"      # Project title
+  title:        "8-bit DEM R2R DAC"      # Project title
   author:       "Eric Fogleman"      # Your name
   discord:      "ejfogleman"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "8-bit segmented mismatch-shaping R2R DAC"      # One line description of what your project does

projects/tt_um_ejfogleman_smsdac/stats/metrics.csv

@@ -1,2 +1,2 @@
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projects/tt_um_ejfogleman_smsdac/tt_um_ejfogleman_smsdac.spef

@@ -1,6 +1,6 @@
 *SPEF "ieee 1481-1999"
 *DESIGN "tt_um_ejfogleman_smsdac"
-*DATE "18:43:49 Thursday April 18, 2024"
+*DATE "22:33:46 Thursday April 18, 2024"
 *VENDOR "The OpenROAD Project"
 *PROGRAM "OpenROAD"
 *VERSION "0889970d1790a2617e69f253221b8bd7626e51dc"