feat: update project tt_um_wokwi_395054564978002945 from x3e/tt06-wok…

…wi-template

Commit: 076114875d418f6a153eeb18b4881e259357d6de
Workflow: https://github.com/x3e/tt06-wokwi-template/actions/runs/8710630655

projects/tt_um_wokwi_395054564978002945/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt06 d9a6d620",
+  "app": "Tiny Tapeout tt06 d5153c3f",
   "repo": "https://github.com/x3e/tt06-wokwi-template",
-  "commit": "0eee2c5bd40d368bf30aa5cf97f05fcf5b4af4d3",
-  "workflow_url": "https://github.com/x3e/tt06-wokwi-template/actions/runs/8674024917",
+  "commit": "076114875d418f6a153eeb18b4881e259357d6de",
+  "workflow_url": "https://github.com/x3e/tt06-wokwi-template/actions/runs/8710630655",
   "sort_id": 1713017034109,
   "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

projects/tt_um_wokwi_395054564978002945/docs/info.md

@@ -7,14 +7,25 @@ You can also include images in this folder and reference them in the markdown. E
 512 kb in size, and the combined size of all images must be less than 1 MB.
 -->
 
+We all  know the hexagon is the bestagon. If the cells in your eyes that catch light are hexagonal, it doesn't make sense that all displays use a square grid. This has to end now. That is why the Bestagon LED matrix driver is born.
+
 ## How it works
 
-It shows a rotating ring on a 7 segment display.
+This circuit can drive a charlieplexed hexagonal LED matrix. This matrix has columns with 3-4-5-4-3 pixels.
 
 ## How to test
 
-Connect a 7 segment display to the output pins, apply a 1Hz clock signal to the input pin. Check the pattern shown in the 7 segment display.
+- Connect the display shown under "External hardware" (or if you want to see if the circuit is functioning: connect a few LEDs between the display output pins randomly)
+- Set the Display Enable pin low. 
+- The Data pin is now sampled on each rising clock edge. The data shall be entered column wise, bottom to top, right to left (in the schematic below, "1" represents the first bit entered).
+  The following data may make you smile: 1001010100001010100
+- Now set the Display Enable pin high.
+- Keep pulsing the clock pin (at least 100Hz is recommended)
 
 ## External hardware
 
-7 segment display on the output pins.
+Charlieplexed hexagonal display:
+
+![Schematic with LED numbering](https://github.com/x3e/tt06-wokwi-template/blob/main/docs/schematic.png?raw=true)
+
+(Maybe add some resistors depending on what LEDs you chose. I recommend blue LEDs because they look cool.

projects/tt_um_wokwi_395054564978002945/info.yaml

@@ -1,21 +1,21 @@
 # Tiny Tapeout project information (Wokwi project)
 project:
   wokwi_id:     395054564978002945       # Set this to the ID of your Wokwi project (the number from the project's URL)
-  title:        "Temporary submission"      # Project title
+  title:        "Bestagon LED matrix driver"      # Project title
   author:       "Marijn"      # Your name
   discord:      "x3ex3e"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "Show rotating ring on 7 segment display"      # One line description of what your project does
+  description:  "Driver for a hexagonal charlieplexed LED matrix"      # One line description of what your project does
   language:     "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     1       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     1000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
+  ui[0]: "Data"
+  ui[1]: "Display Enable"
   ui[2]: ""
   ui[3]: ""
   ui[4]: ""
@@ -24,21 +24,21 @@ pinout:
   ui[7]: ""
 
   # Outputs
-  uo[0]: "7 segment pin 1"
-  uo[1]: "7 segment pin 2"
-  uo[2]: "7 segment pin 3"
-  uo[3]: "7 segment pin 4"
-  uo[4]: "7 segment pin 5"
-  uo[5]: "7 segment pin 6"
-  uo[6]: "7 segment pin 7"
-  uo[7]: "7 segment pin 8"
+  uo[0]: ""
+  uo[1]: ""
+  uo[2]: ""
+  uo[3]: ""
+  uo[4]: ""
+  uo[5]: ""
+  uo[6]: ""
+  uo[7]: ""
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
-  uio[2]: ""
-  uio[3]: ""
-  uio[4]: ""
+  uio[0]: "Display pin 0"
+  uio[1]: "Display pin 1"
+  uio[2]: "Display pin 2"
+  uio[3]: "Display pin 3"
+  uio[4]: "Display pin 4"
   uio[5]: ""
   uio[6]: ""
   uio[7]: ""

projects/tt_um_wokwi_395054564978002945/stats/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_wokwi_395054564978002945,wokwi,flow completed,0h0m45s0ms,0h0m31s0ms,4678.43553115838,0.01795472,2339.21776557919,1.04,3.3682299999999996,487.73,31,0,0,0,0,0,0,0,0,0,0,-1,-1,654,182,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,574023.0,0.0,0.88,0.26,1.27,1.02,-1,42,77,42,77,0,0,0,5,0,1,0,0,1,1,0,1,8,4,2,1223,225,0,244,42,1734,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_wokwi_395054564978002945,wokwi,flow completed,0h0m52s0ms,0h0m36s0ms,15928.95907037258,0.01795472,7964.47953518629,6.82,10.6205,489.91,106,0,0,0,0,0,0,0,1,1,0,-1,-1,2412,802,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,1480703.0,0.0,5.94,2.87,0.86,0.47,-1,270,305,236,271,0,0,0,64,15,4,1,0,19,0,0,19,26,25,4,1146,225,0,238,143,1752,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_wokwi_395054564978002945/stats/synthesis-stats.txt

@@ -3,22 +3,27 @@
 
 === tt_um_wokwi_395054564978002945 ===
 
-   Number of wires:                 15
-   Number of wire bits:             50
-   Number of public wires:          13
-   Number of public wire bits:      48
+   Number of wires:                 90
+   Number of wire bits:            125
+   Number of public wires:          38
+   Number of public wire bits:      73
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 31
-     sky130_fd_sc_hd__buf_1          2
-     sky130_fd_sc_hd__buf_2          7
-     sky130_fd_sc_hd__conb_1        17
-     sky130_fd_sc_hd__dfxtp_2        1
-     sky130_fd_sc_hd__inv_2          1
-     sky130_fd_sc_hd__mux2_2         1
-     sky130_fd_sc_hd__or2_2          1
-     sky130_fd_sc_hd__xor2_2         1
+   Number of cells:                106
+     sky130_fd_sc_hd__a211o_2        3
+     sky130_fd_sc_hd__a21o_2         4
+     sky130_fd_sc_hd__a221o_2        1
+     sky130_fd_sc_hd__a22o_2         4
+     sky130_fd_sc_hd__and2_2         3
+     sky130_fd_sc_hd__buf_1         23
+     sky130_fd_sc_hd__buf_2         10
+     sky130_fd_sc_hd__conb_1        14
+     sky130_fd_sc_hd__dfrtp_2        4
+     sky130_fd_sc_hd__dfstp_2        1
+     sky130_fd_sc_hd__dfxtp_2       19
+     sky130_fd_sc_hd__mux2_2        19
+     sky130_fd_sc_hd__or4_2          1
 
-   Chip area for module '\tt_um_wokwi_395054564978002945': 165.158400
+   Chip area for module '\tt_um_wokwi_395054564978002945': 1086.041600