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feat: update project tt_um_toivoh_retro_console from toivoh/tt06-retr…
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…o-console

Commit: 0ba2cb6a3082c664f4839961a3639472d2e525c6
Workflow: https://github.com/toivoh/tt06-retro-console/actions/runs/8726019472
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Apr 17, 2024
1 parent e699f42 commit 805a1ac
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6 changes: 3 additions & 3 deletions projects/tt_um_toivoh_retro_console/commit_id.json
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{
"app": "Tiny Tapeout tt06 eed83093",
"app": "Tiny Tapeout tt06 bc500a3a",
"repo": "https://github.com/toivoh/tt06-retro-console",
"commit": "7c88f17702e6267ea4456c2a439b454f4d8fc267",
"workflow_url": "https://github.com/toivoh/tt06-retro-console/actions/runs/8716562047",
"commit": "0ba2cb6a3082c664f4839961a3639472d2e525c6",
"workflow_url": "https://github.com/toivoh/tt06-retro-console/actions/runs/8726019472",
"sort_id": 1711967951372,
"openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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132 changes: 130 additions & 2 deletions projects/tt_um_toivoh_retro_console/docs/info.md
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Expand Up @@ -227,8 +227,136 @@ Available registers:

## Using the PPU
The PPU is almost completely controlled through the VRAM (video RAM) contents.
The copper is restarted when a new frame begins, and starts to read instructions at address `0xfffe`.

The copper is restarted when a new frame begins, and starts to read instructions at address `0xfffe`. Copper instructions can write PPU registers; using the copper is the only way to write and initialize these registers.

The PPU registers in turn control the display of tile planes and sprites.

### PPU registers
The PPU has 32 PPU registers, which control different aspects of its operation.
Each register has up to 9 bits. The registers are laid out as follows:

Address Category Contents
8 7 6 5 4 3 2 1 0
0 - 15 pal0-pal15 | r2 r1 rb0 g2 g1 g0 b2 b1 | X |
16 scroll | scroll_x0 |
17 . | X | scroll_y0 |
18 . | scroll_x1 |
19 . | X | scroll_y1 |
20 copper_ctrl| cmp_x |
21 . | cmp_y |
22 . | jump_lsb |
23 . | jump_msb |
24 base_addr | base_sorted |
25 . | base_oam |
26 . | base_map1 | base_map0 | X |
27 . | X |b_tile_s | b_tile_p | X |
28 gfxmode1 | r_xe_hsync | r_x0_fp |
29 gfxmode2 |vpol|hpol| vsel | r_x0_bp |
30 gfxmode3 | r_xe_active |
31 displaymask| X |lspr|lpl1|lpl0|dspr|dpl1|dpl0|

where `X` means that the bit(s) in question are ignored.

Initial values:
- The `gfxmode` registers are initialized to `320x240` output (640x480 VGA output; pixels are always doubled in both directions before VGA output).
- The `displaymask` register is initialized to load and display sprites as well as both tile planes (initial value `0b111111`).
- The other registers, except the `copper_ctrl` category, need to be initialized after reset.

Each PPU register is described in the appropriate section:
- Palette (`pal0-pal15`)
- Tile planes (`scroll`, `base_map0`, `base_map1`, `b_tile_p`, `lpl0`, `lpl1`, `dpl0`, `dpl1`)
- Sprites (`base_sorted`, `base_oam`, `b_tile_s`, `lspr`, `dspr`)
- Copper (`copper_ctrl`)
- Graphics mode `gfxmode1-gfxmode3`)

### Palette
The PPU has a palette of 16 colors, each specified by 8 bits, which map to a 9 bit RGB333 color according to

R = {r2, r1, rb0}
G = {g2, g1, g0}
B = {b2, b1, rb0}

where the least significant bit is shared between the red and blue channels.
Each palette color is set by writing the corresponding `palN` register. The instant when a palette color register is written, its color value will be used to display the current pixel if it is inside the active display area.

Tile and sprite graphics typically use 2 bits per pixel. They have a 4 bit `pal` attribute that specifies the mapping from tile pixels to paletter colors according to:

pal color 0 color 1 color 2 color 3
0 0 1 2 3
4 4 5 6 7
8 8 9 10 11
12 12 13 14 15
2 2 3 4 5
6 6 7 8 9
10 10 11 12 13
14 14 15 0 1
1 0 4 8 12
5 1 5 9 13
9 2 6 10 14
13 3 7 11 15
3 8 12 1 5
7 9 13 2 6
11 10 14 3 7
15 ---------------- 16 color mode ----------------

_Note that color 0 is transparent unless the `always_opaque` bit of the sprite/tile is set._
If no tile or sprite covers a given pixel, palette color 0 is used as background color.

In 16 color mode, two horizontally consecutive 2 bit pixels are used to form one 4 bit pixel.
- For 16 color tiles, each pixel is twice as wide to preserve the same total width.
- 16 color sprites are half as wide (8 pixels instead of 16).

### Tile graphic format
Tile planes and sprites are based on 8x8 pixel graphic tiles with 2 bits/pixel.
Each graphic tile is stored in 8 consecutive 16 bit words; one per line.
Within each line, the first pixel is stored in the bottom two bits, then the next pixel, and so on.

### Tile planes
The PPU supports two independently scrolling tile planes. Plane 0 is in front of plane 1.
Four `display_mask` bits control the behavior of the tile planes:
- When `dpl0` (`dpl1`) is cleared, plane 0 (1) is not displayed.
- When `lpl0` (`lpl1`) is cleared, no data for plane 0 (1) is loaded.

If a planes is not to be displayed, its `lplN` bit can be cleared to free up more read bandwidth for the sprites and copper. The plane's `lplN` bit should be set at least 16 pixels before the plane should be displayed.

The VRAM addresses used for the tile planes are

plane_tiles_base = b_tile_p << 14
map0_base = base_map0 << 12
map1_base = base_map1 << 12

The `scroll` registers specify the scroll position of the respective plane (TODO: describe offset).

The tile map for each plane is 64x64 tiles, and is stored row by row.
Each map entry is 16 bits:

15 - 12 11 10 - 0
| pal | always_opaque | tile_index |

where the tile is read from word address

tile_addr = plane_tiles_base + (tile_index << 3)

### Sprites
Each sprite can be 16x8 pixels (4 color) or 8x8 pixels (16 color).
The PPU supports up to 64 simultaneous sprites in oam memory, but only 4 can overlap at the same time. Once a sprite is done for the scan line, the PPU can load a new sprite into the same slot, to display later on the same scan line, but it takes a number of pixels (partially depending on how much memory traffic is used by the tile planes and the copper.) More than 64 sprites can be displayed in a single frame by using the copper to change base addresses mid frame.

Two `display_mask` bits control the behavior of the sprite display:
- When `dspr` is cleared, no sprites are displayed.
- When `lspr` is cleared, no data for sprites is loaded.

It will take some time `lspr` is set before new sprites are completely loaded and can be displayed.

The VRAM addresses used for sprite display are

sprite_tiles_base = b_tile_s << 14
sorted_base = base_sorted << 6
oam_base = base_oam << 7


## How to test
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2 changes: 1 addition & 1 deletion projects/tt_um_toivoh_retro_console/stats/metrics.csv
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_toivoh_retro_console,wokwi,flow completed,0h11m2s0ms,0h8m48s0ms,132041.69680019663,0.1148576576,66020.84840009832,64.3,69.7091,780.58,6582,0,0,0,0,0,0,0,4,4,0,-1,-1,186063,51385,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,119673838.0,0.0,54.31,46.97,12.75,7.24,-1,5137,9005,609,4431,0,0,0,5913,224,68,180,307,851,405,75,905,1196,1196,25,3320,1577,27,2516,7583,15023,110873.8368,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,20.84,47.98464491362764,19.84,1,50,153.18,153.6,0.3,1,10,0.68,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_toivoh_retro_console,wokwi,flow completed,0h10m18s0ms,0h8m12s0ms,132529.25680420632,0.1148576576,66264.62840210316,64.3,69.8242,780.97,6582,0,0,0,0,0,0,0,5,5,0,-1,-1,187432,51327,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,121936635.0,0.0,54.74,47.32,13.33,7.31,-1,5137,9005,609,4431,0,0,0,5913,224,68,180,307,851,405,75,905,1196,1196,25,3387,1577,37,2564,7611,15176,110873.8368,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,20.84,47.98464491362764,19.84,1,50,153.18,153.6,0.3,1,10,0.66,0,sky130_fd_sc_hd,AREA 0
Binary file modified projects/tt_um_toivoh_retro_console/tt_um_toivoh_retro_console.gds
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125 changes: 62 additions & 63 deletions projects/tt_um_toivoh_retro_console/tt_um_toivoh_retro_console.lef
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Expand Up @@ -283,7 +283,7 @@ MACRO tt_um_toivoh_retro_console
PIN uio_out[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 55.510 224.760 55.810 225.760 ;
Expand All @@ -292,7 +292,7 @@ MACRO tt_um_toivoh_retro_console
PIN uio_out[2]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 51.830 224.760 52.130 225.760 ;
Expand All @@ -301,7 +301,7 @@ MACRO tt_um_toivoh_retro_console
PIN uio_out[3]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 48.150 224.760 48.450 225.760 ;
Expand All @@ -310,7 +310,7 @@ MACRO tt_um_toivoh_retro_console
PIN uio_out[4]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 44.470 224.760 44.770 225.760 ;
Expand Down Expand Up @@ -355,7 +355,7 @@ MACRO tt_um_toivoh_retro_console
PIN uo_out[1]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 84.950 224.760 85.250 225.760 ;
Expand All @@ -373,7 +373,7 @@ MACRO tt_um_toivoh_retro_console
PIN uo_out[3]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 77.590 224.760 77.890 225.760 ;
Expand All @@ -391,7 +391,7 @@ MACRO tt_um_toivoh_retro_console
PIN uo_out[5]
DIRECTION OUTPUT TRISTATE ;
USE SIGNAL ;
ANTENNADIFFAREA 0.445500 ;
ANTENNADIFFAREA 0.891000 ;
PORT
LAYER met4 ;
RECT 70.230 224.760 70.530 225.760 ;
Expand Down Expand Up @@ -461,64 +461,63 @@ MACRO tt_um_toivoh_retro_console
LAYER li1 ;
RECT 2.760 2.635 506.000 223.125 ;
LAYER met1 ;
RECT 2.760 2.480 506.390 224.020 ;
RECT 2.760 2.480 506.300 223.280 ;
LAYER met2 ;
RECT 4.700 2.535 506.360 224.925 ;
RECT 4.700 2.535 504.980 224.245 ;
LAYER met3 ;
RECT 6.510 2.555 503.175 224.905 ;
LAYER met4 ;
RECT 4.690 224.360 7.270 224.905 ;
RECT 8.370 224.360 10.950 224.905 ;
RECT 12.050 224.360 14.630 224.905 ;
RECT 15.730 224.360 18.310 224.905 ;
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RECT 115.090 224.360 117.670 224.905 ;
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RECT 3.990 223.680 496.505 224.360 ;
RECT 3.990 19.215 17.880 223.680 ;
RECT 20.280 19.215 94.680 223.680 ;
RECT 97.080 19.215 171.480 223.680 ;
RECT 173.880 19.215 248.280 223.680 ;
RECT 250.680 19.215 325.080 223.680 ;
RECT 327.480 19.215 401.880 223.680 ;
RECT 404.280 19.215 478.680 223.680 ;
RECT 481.080 19.215 496.505 223.680 ;
RECT 6.510 2.555 492.595 224.225 ;
LAYER met4 ;
RECT 4.690 224.360 7.270 224.760 ;
RECT 8.370 224.360 10.950 224.760 ;
RECT 12.050 224.360 14.630 224.760 ;
RECT 15.730 224.360 18.310 224.760 ;
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RECT 30.450 224.360 33.030 224.760 ;
RECT 34.130 224.360 36.710 224.760 ;
RECT 37.810 224.360 40.390 224.760 ;
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RECT 48.850 224.360 51.430 224.760 ;
RECT 52.530 224.360 55.110 224.760 ;
RECT 56.210 224.360 58.790 224.760 ;
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RECT 63.570 224.360 66.150 224.760 ;
RECT 67.250 224.360 69.830 224.760 ;
RECT 70.930 224.360 73.510 224.760 ;
RECT 74.610 224.360 77.190 224.760 ;
RECT 78.290 224.360 80.870 224.760 ;
RECT 81.970 224.360 84.550 224.760 ;
RECT 85.650 224.360 88.230 224.760 ;
RECT 89.330 224.360 91.910 224.760 ;
RECT 93.010 224.360 95.590 224.760 ;
RECT 96.690 224.360 99.270 224.760 ;
RECT 100.370 224.360 102.950 224.760 ;
RECT 104.050 224.360 106.630 224.760 ;
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RECT 148.210 224.360 150.790 224.760 ;
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RECT 327.480 16.495 401.880 223.680 ;
RECT 404.280 16.495 469.825 223.680 ;
END
END tt_um_toivoh_retro_console
END LIBRARY
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