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feat: update project tt_um_scorbetta_goa from scorbetta/tt06-scorbett…
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…a-goa

Commit: 0206e8503731efd8848b47a48e6e03e5778bc27c
Workflow: https://github.com/scorbetta/tt06-scorbetta-goa/actions/runs/8523560553
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Apr 2, 2024
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6 changes: 3 additions & 3 deletions projects/tt_um_scorbetta_goa/commit_id.json
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{
"app": "Tiny Tapeout tt06 316141d7",
"app": "Tiny Tapeout tt06 b544d27d",
"repo": "https://github.com/scorbetta/tt06-scorbetta-goa",
"commit": "996df0bef9c80315e4839468e427cea091685a14",
"workflow_url": "https://github.com/scorbetta/tt06-scorbetta-goa/actions/runs/8359427296",
"commit": "0206e8503731efd8848b47a48e6e03e5778bc27c",
"workflow_url": "https://github.com/scorbetta/tt06-scorbetta-goa/actions/runs/8523560553",
"sort_id": 1711018340303,
"openlane_version": "OpenLane f691c8c0712ca6c6645e3fd548985b3cbcf08c78",
"pdk_version": "open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571"
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136 changes: 63 additions & 73 deletions projects/tt_um_scorbetta_goa/docs/info.md
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chip](https://github.com/scorbetta/CORTEZ) targeting the Tiny Tapeout 6 run. The `grogu` part comes
from the register file design utilities [grogu](https://github.com/scorbetta/grogu).

The `GOA` design is made of a single neuron with 2 (two) inputs. The register file thus contains 4
(four) registers: 2 (two) contain values for the weights, 1 (one) contains value for the bias and 1
(one) contains the result computed by the neuron arithmetic core. The neuron works on 8 (eight) bits
fixed-point arithmetic with 5 (five) reserved for the fraction.
The `GOA` design is made of a single neuron with 2 (two) inputs. The register file contains a number
of registers for control and observation. The neuron core works on 8 (eight) bits fixed-point
arithmetic with 5 (five) reserved for the fraction.

# Neuron internals
The next figure shows the simplified block diargram of the Neuron.
The next figure shows the simplified block diagram of the Neuron.

![Neuron architecture](Neuron.png)

Expand Down Expand Up @@ -71,83 +70,74 @@ Examples of Write and Read accesses are shown.

![Read access](SCI_Read.png)

# Pinout
The top-level `tt_um_scorbetta_goa` adheres to the following pinout:
## Network emulation
A twisted use of the single-neuron design can emulate an entire network made of a number of layers,
each with a number of neuron. This is doable thanks to the way the neuron is designed. Basically,
the 2-inputs neuron is repeadetely fed with iterative data, coming from either the external world
(i.e., input values) or intermediate results (i.e., from the inner core). Mathematically, the MAC
operation is distributed in time.

![Network emulation](NetworkEmulation.png)

# Pinout
| PIN | DIRECTION | ROLE |
|-|-|-|
| `ui_in[0]` | input | Core clock, generated by the FPGA |
| `ui_in[1]` | input | Active-low core reset |
| `ui_in[2]` | input | `SCI_CSN` |
| `ui_in[3]` | input | `SCI_REQ` |
| `ui_in[4]` | input | Load value in |
| `ui_in[5]` | input | Value in |
| `ui_in[6]` | input | Shift result out |
| `ui_in[7]` | input | Neuron trigger |
| `uo_out[0]` | output | `SCI_RESP` |
| `uo_out[1]` | output | `SCI_ACK` |
| `uo_out[2]` | output | Result out |
| `uo_out[3]` | output | Neuron ready |
| `uo_out[4]` | output | Neuron done |
| `uo_out[5]` | output | Debug counter [5] |
| `uo_out[6]` | output | Debug counter [6] |
| `uo_out[7]` | output | Debug counter [7] |
| `uio_in[7:0]` | input | Unused |
| `uio_out[7:0]` | output | Unused |
| `uio_oe[7:0]` | output | Unused, tied to 8'h0 |
| `ena` | input | 1'b1 when design is enabled |
| `clk` | input | RP2040 clock, used for debug |
| `rst_n`| input | Active-low reset |
| `ui_in[0]` | input | FPGA clock |
| `ui_in[1]` | input | Active-low FPGA reset |
| `ui_in[2]` | input | Loopback data |
| `ui_in[3]` | input | Unused |
| `ui_in[4]` | input | Unused |
| `ui_in[5]` | input | Unused |
| `ui_in[6]` | input | Debug select [0] |
| `ui_in[7]` | input | Debug select [1] |
| `uo_out[0]` | output | Shared debug output dbug_out[0] |
| `uo_out[1]` | output | Shared debug output dbug_out[1] |
| `uo_out[2]` | output | Shared debug output dbug_out[2] |
| `uo_out[3]` | output | Shared debug output dbug_out[3] |
| `uo_out[4]` | output | Shared debug output dbug_out[4] |
| `uo_out[5]` | output | Shared debug output dbug_out[5] |
| `uo_out[6]` | output | Shared debug output dbug_out[6] |
| `uo_out[7]` | output | Shared debug output dbug_out[7] |
| `uio_in[0]` | input | SCI_CSN |
| `uio_in[1]` | input | SCI_REQ |
| `uio_out[2]` | output | SCI_RESP |
| `uio_out[3]` | output | SCI_ACK |
| `uio_out[4]` | input | Unused, configured as input |
| `uio_out[5]` | input | Unused, configured as input |
| `uio_out[6]` | input | Unused, configured as input |
| `uio_out[7]` | input | Unused, configured as input |

Debug signals are mapped to output pins `uo_out`. In total, 32 (thirty-two) signals are exposed to
the debug interface. Inputs `ui_in[7:6]` are used to control which ones, according to the following
table.

![Debug signals mux](DebugSignalsMux.png)

# Configuration
The configuration of the neuron is implemented by means of local registers that hold the values for
the weights and the bias. In addition, control registers are used to trigger the neuron operations.
All resigsters are 8 (eight) bits wide

| REGISTER | OFFSET | TYPE | CONTENTS |
|-|-|-|-|
| `WEIGHT_0` | 0x0 | R/W | Weight of input #0 |
| `WEIGHT_1` | 0x1 | R/W | Weight of input #1 |
| `BIAS` | 0x2 | R/W | Bias |
| `VALUE_IN` | 0x3 | R/W | Input value |
| `CTRL` | 0x4 | R/W | Control register |
| `STATUS` | 0x5 | R | Status register |
| `RESULT` | 0x6 | R | Neuron solution |
| `MULT_RESULT` | 0x7 | R | Intermediate multiplie result |
| `ADD_RESULT` | 0x8 | R | Intermediate adder result w/o bias |
| `BIAS_ADD_RESULT` | 0x9 | R | Intermediate adder result w/ bias |

# External hardware
The main clock `clk` is generated by the on-board RP2040 chip. It is used solely for debug purposes.
It drives an 8 (eight) bit counter, whose 3 (three) MSBs are rerouted to `uo_out` (please refer to
the pinout table).
It is mirrored to `uo_out[1]`.

The core clock is instead drawn from `ui_in[0]`. This is generated by an FPGA residing on an
external board. `ui_in[0]` and `clk` are mesochronous, and they never interact. The use of an
external clock is required, since the SCI interface (also driven by the FPGA) needs proper
synchronization.

## FPGA control loop
The external FPGA runs a simple control loop:

```
// Wait for ready signal
wait_for(uo_out[3] == 1);
// Basic connectivity test
repeat(10) {
sci_write_debug_reg();
sci_read_debug_reg();
verify();
}
// Configure weights and bias
sci_write_weights();
sci_write_bias();
// Stimuli loop
forever {
// Send random values one at a time
repeat(2) {
load_value(random);
wait_for(uo_out[3] == 1);
pulse(ui_in[7]);
}
// Wait for result
wait_for(uo_out[4] == 1);
shift_result();
// Do something with result
...
}
```

# How to test
TBD
external board. `ui_in[0]` and `clk` are mesochronous, and they never interact.

The use of an external clock is required, since the SCI interface (also driven by the FPGA) needs
proper synchronization. The FPGA also drives the active-low core reset through `ui_in[1]`. All
control and status information is sent to and retrieved from the ASIC through the SCI interface.
39 changes: 20 additions & 19 deletions projects/tt_um_scorbetta_goa/info.yaml
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Expand Up @@ -23,6 +23,7 @@ project:
- "FIXED_POINT_ACT_FUN.v"
- "RW_REG.v"
- "RO_REG.v"
- "DELTA_REG.v"
- "REGPOOL.v"
- "D_FF_EN.v"
- "PISO_BUFFER.v"
Expand All @@ -39,29 +40,29 @@ project:
pinout:
# Inputs
ui[0]: "FPGA clock"
ui[1]: "FPGA reset"
ui[2]: "SCI_CSN"
ui[3]: "SCI_REQ"
ui[4]: "Input value load-in"
ui[5]: "Input value"
ui[6]: "Output value shift-out"
ui[7]: "Neuron trigger"
ui[1]: "Active-low FPGA reset"
ui[2]: "Loopback data"
ui[3]: ""
ui[4]: ""
ui[5]: ""
ui[6]: "Debug select [0]"
ui[7]: "Debug select [1]"

# Outputs
uo[0]: "SCI_RESP"
uo[1]: "SCI_ACK"
uo[2]: "Output value"
uo[3]: "Neuron ready"
uo[4]: "Neuron done"
uo[5]: ""
uo[6]: ""
uo[7]: ""
uo[0]: "Shared debug output dbug_out[0]"
uo[1]: "Shared debug output dbug_out[1]"
uo[2]: "Shared debug output dbug_out[2]"
uo[3]: "Shared debug output dbug_out[3]"
uo[4]: "Shared debug output dbug_out[4]"
uo[5]: "Shared debug output dbug_out[5]"
uo[6]: "Shared debug output dbug_out[6]"
uo[7]: "Shared debug output dbug_out[7]"

# Bidirectional pins
uio[0]: ""
uio[1]: ""
uio[2]: ""
uio[3]: ""
uio[0]: "SCI_CSN"
uio[1]: "SCI_REQ"
uio[2]: "SCI_RESP"
uio[3]: "SCI_ACK"
uio[4]: ""
uio[5]: ""
uio[6]: ""
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2 changes: 1 addition & 1 deletion projects/tt_um_scorbetta_goa/stats/metrics.csv
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
/work/src,tt_um_scorbetta_goa,wokwi,flow completed,0h13m43s0ms,0h13m14s0ms,149487.1543527273,0.01795472,74743.57717636364,78.2,88.74220000000001,634.8,1168,0,0,0,0,0,0,0,16,16,0,-1,-1,51261,10991,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,14466585.0,0.0,74.64,74.44,54.17,60.97,-1,1401,2411,441,1353,0,0,0,1220,61,19,54,73,117,176,97,51,192,174,19,323,225,9,410,1342,2309,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,41.0,24.390243902439025,40,1,50,26.520,38.870,0.3,1,10,0.9,0,sky130_fd_sc_hd,AREA 0
/work/src,tt_um_scorbetta_goa,wokwi,flow completed,0h4m2s0ms,0h3m33s0ms,153497.24195086307,0.01795472,76748.62097543154,86.09,86.914,574.05,1265,0,0,0,0,0,0,0,2,2,0,-1,-1,33473,9865,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,17442533.0,0.0,59.58,51.03,16.98,11.88,-1,1685,3015,545,1782,0,0,0,1426,80,46,54,78,203,169,100,48,219,183,20,323,225,5,433,1378,2364,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,41.0,24.390243902439025,40,1,50,26.520,38.870,0.3,1,10,0.9,0,sky130_fd_sc_hd,AREA 0
114 changes: 60 additions & 54 deletions projects/tt_um_scorbetta_goa/stats/synthesis-stats.txt
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80. Printing statistics.
81. Printing statistics.

=== tt_um_scorbetta_goa ===

Number of wires: 1152
Number of wire bits: 1187
Number of public wires: 196
Number of public wire bits: 231
Number of wires: 1249
Number of wire bits: 1284
Number of public wires: 224
Number of public wire bits: 259
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1168
sky130_fd_sc_hd__a211o_2 2
sky130_fd_sc_hd__a211oi_2 2
sky130_fd_sc_hd__a21bo_2 10
sky130_fd_sc_hd__a21boi_2 1
sky130_fd_sc_hd__a21o_2 39
Number of cells: 1265
sky130_fd_sc_hd__a2111o_2 1
sky130_fd_sc_hd__a211o_2 7
sky130_fd_sc_hd__a211oi_2 1
sky130_fd_sc_hd__a21bo_2 5
sky130_fd_sc_hd__a21boi_2 2
sky130_fd_sc_hd__a21o_2 30
sky130_fd_sc_hd__a21oi_2 30
sky130_fd_sc_hd__a221o_2 6
sky130_fd_sc_hd__a22o_2 11
sky130_fd_sc_hd__a221o_2 18
sky130_fd_sc_hd__a22o_2 37
sky130_fd_sc_hd__a22oi_2 8
sky130_fd_sc_hd__a2bb2o_2 1
sky130_fd_sc_hd__a31o_2 13
sky130_fd_sc_hd__a32o_2 2
sky130_fd_sc_hd__and2_2 30
sky130_fd_sc_hd__and2b_2 14
sky130_fd_sc_hd__and3_2 43
sky130_fd_sc_hd__and3b_2 6
sky130_fd_sc_hd__and4_2 10
sky130_fd_sc_hd__and4b_2 8
sky130_fd_sc_hd__buf_1 123
sky130_fd_sc_hd__buf_2 8
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__dfxtp_2 185
sky130_fd_sc_hd__inv_2 23
sky130_fd_sc_hd__mux2_2 82
sky130_fd_sc_hd__mux4_2 3
sky130_fd_sc_hd__nand2_2 83
sky130_fd_sc_hd__nand3_2 3
sky130_fd_sc_hd__a2bb2o_2 8
sky130_fd_sc_hd__a311o_2 4
sky130_fd_sc_hd__a311oi_2 1
sky130_fd_sc_hd__a31o_2 14
sky130_fd_sc_hd__a31oi_2 2
sky130_fd_sc_hd__a32o_2 9
sky130_fd_sc_hd__a32oi_2 1
sky130_fd_sc_hd__and2_2 50
sky130_fd_sc_hd__and2b_2 23
sky130_fd_sc_hd__and3_2 34
sky130_fd_sc_hd__and3b_2 3
sky130_fd_sc_hd__and4_2 11
sky130_fd_sc_hd__and4b_2 7
sky130_fd_sc_hd__and4bb_2 3
sky130_fd_sc_hd__buf_1 150
sky130_fd_sc_hd__buf_2 2
sky130_fd_sc_hd__conb_1 14
sky130_fd_sc_hd__dfxtp_2 213
sky130_fd_sc_hd__inv_2 24
sky130_fd_sc_hd__mux2_2 103
sky130_fd_sc_hd__nand2_2 90
sky130_fd_sc_hd__nand3_2 2
sky130_fd_sc_hd__nand4_2 2
sky130_fd_sc_hd__nor2_2 52
sky130_fd_sc_hd__nor2_2 56
sky130_fd_sc_hd__nor2b_2 1
sky130_fd_sc_hd__nor3_2 7
sky130_fd_sc_hd__o211a_2 48
sky130_fd_sc_hd__o211ai_2 2
sky130_fd_sc_hd__o21a_2 27
sky130_fd_sc_hd__o21ai_2 33
sky130_fd_sc_hd__nor3_2 4
sky130_fd_sc_hd__nor4_2 1
sky130_fd_sc_hd__nor4b_2 2
sky130_fd_sc_hd__o211a_2 33
sky130_fd_sc_hd__o211ai_2 1
sky130_fd_sc_hd__o21a_2 24
sky130_fd_sc_hd__o21ai_2 29
sky130_fd_sc_hd__o21ba_2 10
sky130_fd_sc_hd__o21bai_2 2
sky130_fd_sc_hd__o221a_2 18
sky130_fd_sc_hd__o22a_2 3
sky130_fd_sc_hd__o22ai_2 2
sky130_fd_sc_hd__o2bb2a_2 7
sky130_fd_sc_hd__o31a_2 2
sky130_fd_sc_hd__o32a_2 1
sky130_fd_sc_hd__o41a_2 1
sky130_fd_sc_hd__or2_2 58
sky130_fd_sc_hd__or2b_2 14
sky130_fd_sc_hd__or3_2 10
sky130_fd_sc_hd__or3b_2 2
sky130_fd_sc_hd__or4_2 1
sky130_fd_sc_hd__or4b_2 1
sky130_fd_sc_hd__xnor2_2 70
sky130_fd_sc_hd__xor2_2 32
sky130_fd_sc_hd__o21bai_2 1
sky130_fd_sc_hd__o221a_2 4
sky130_fd_sc_hd__o22a_2 5
sky130_fd_sc_hd__o22ai_2 1
sky130_fd_sc_hd__o2bb2a_2 4
sky130_fd_sc_hd__o31a_2 3
sky130_fd_sc_hd__o31ai_2 1
sky130_fd_sc_hd__o32a_2 6
sky130_fd_sc_hd__or2_2 38
sky130_fd_sc_hd__or2b_2 13
sky130_fd_sc_hd__or3_2 6
sky130_fd_sc_hd__or3b_2 3
sky130_fd_sc_hd__or4_2 2
sky130_fd_sc_hd__xnor2_2 80
sky130_fd_sc_hd__xor2_2 28

Chip area for module '\tt_um_scorbetta_goa': 12449.440000
Chip area for module '\tt_um_scorbetta_goa': 13704.393600

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