Fixing tt-um-lisa table format (I think).

TinyTapeout · Apr 27, 2024 · 31e2d9f · 31e2d9f
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diff --git a/projects/tt_um_lisa/docs/debug_uart.png b/projects/tt_um_lisa/docs/debug_uart.png
diff --git a/projects/tt_um_lisa/docs/debug_uart.txt b/projects/tt_um_lisa/docs/debug_uart.txt
@@ -1,18 +1,18 @@
-           .rx1.    |\                                     +--------------------------------+
-  ui_in[3]--------*-+1|                                    |{pt}      Debug Control         |
-           .rx2.  | | |                               .rx. |  +------+  +---------------+   |  Debug
- uio_in[4]------*-|-+2+------------------------------------|->|      |  |               |   |   Bus
-           .rx3.| | | |                               .tx. |  |      +--+----- FSM  ----+---|----------> 
- uio_in[6]----*-|-|-+3|             +---------------<------|--+      |  |       |       |   |           
-              | | | |/          .1. |                      |  | UART |  |  {cl} |       |   |
-              | | |  |Port    +-----|--+''\__________      |  |      |  +-------+-------+   |
-              | | |  | Sel    | .2. *--+__/ uio_out[4]     |  |      |          |  {pr}     |
-              V V V  *--------*-----|--+''\__________      |  |      |  +-------+-------+   | Registers 
-       +-------------+-+      | .3. *--+__/ uio_out[5]  +--|->| {pb} |  |   Registers   +---|----------> 
-       | {pt}          |      +-----|--+''\__________   |  |  +---+--+  +---------------+   |  
-       |    ^Debug^    | .Baud Set. +--+__/ uio_out[5]  |  |      +-------------------------|----------> 
-       |  ^Autobaud^   +--------------------------------+  +--------------------------------+  Uart 
-       +---------------+                                                                    Passthrough
+           .rx1.    |\                                        +--------------------------------+
+  ui_in[3]--------*-+1|                                       |{pt}      Debug Control         |
+           .rx2.  | | |                                  .rx. |  +------+  +---------------+   |  Debug
+ uio_in[4]------*-|-+2+---------------------------------------|->|      |  |               |   |   Bus
+           .rx3.| | | |                                  .tx. |  |      +--+----- FSM  ----+---|----------> 
+ uio_in[6]----*-|-|-+3|                +---------------<------|--+      |  |       |       |   |           
+              | | | |/        .1.      |                      |  | UART |  |  {cl} |       |   |
+              | | |  |Port  +----------|--+''\__________      |  |      |  +-------+-------+   |
+              | | |  | Sel  | .2.      *--+__/ uio_out[4]     |  |      |          |  {pr}     |
+              V V V  *------*-----)''\ +--+''\__________      |  |      |  +-------+-------+   | Registers 
+       +-------------+-+    | .3. )   +---+__/ uio_out[5]  +--|->| {pb} |  |   Registers   +---|----------> 
+       | {pt}          |    +-----)__/                     |  |  +---+--+  +---------------+   |  
+       |    ^Debug^    | .Baud Set.                        |  |      +-------------------------|----------> 
+       |  ^Autobaud^   +-----------------------------------+  +--------------------------------+  Uart 
+       +---------------+                                                                       Passthrough
                                <h4>Debug Connectivity and Autobaud</h4>
 
 {:FILE scale 0.8 theme light font-size 10}