feat: update project tt_um_MichaelBell_tinyQV from MichaelBell/tt06-t…

…inyQV

Commit: 7367f610209e076eb86b652e5eb8b5b548f8c4ba
Workflow: https://github.com/MichaelBell/tt06-tinyQV/actions/runs/7979211279

projects/tt_um_MichaelBell_tinyQV/LICENSE

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projects/tt_um_MichaelBell_tinyQV/commit_id.json

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+{
+  "app": "Tiny Tapeout tt06 e8c5040d",
+  "repo": "https://github.com/MichaelBell/tt06-tinyQV",
+  "commit": "7367f610209e076eb86b652e5eb8b5b548f8c4ba",
+  "workflow_url": "https://github.com/MichaelBell/tt06-tinyQV/actions/runs/7979211279",
+  "sort_id": 1708463615892,
+  "openlane_version": "OpenLane f691c8c0712ca6c6645e3fd548985b3cbcf08c78",
+  "pdk_version": "open_pdks e0f692f46654d6c7c99fc70a0c94a080dab53571"
+}

projects/tt_um_MichaelBell_tinyQV/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+# How it works
+
+TinyQV is a small Risc-V SoC, implementing the RV32EC instruction set, with a couple of caveats:
+
+* Addresses are 28-bits
+* gp is hardcoded to 0x1000400, tp is hardcoded to 0x8000000.
+
+Instructions are read using QSPI from Flash, and a QSPI PSRAM is used for memory.  The QSPI clock and data lines are shared between the flash and the RAM, so only one can be accessed simultaneously.
+
+Code can only be executed from flash.  Data can be read from flash and RAM, and written to RAM.
+
+The SoC includes a UART and an SPI controller.
+
+## Address map
+
+| Address range | Device |
+| ------------- | ------ |
+| 0x0000000 - 0x0FFFFFF | Flash |
+| 0x1000000 - 0x17FFFFF | RAM A |
+| 0x1800000 - 0x1FFFFFF | RAM B |
+| 0x8000000 - 0x8000007 | GPIO  |
+| 0x8000010 - 0x8000017 | UART |
+| 0x8000020 - 0x8000027 | SPI |
+
+### GPIO
+
+| Register | Address | Description |
+| -------- | ------- | ----------- |
+| OUT      | 0x8000000 (W) | Bits 6 and 7 control out6 and out7 |
+| OUT      | 0x8000000 (R) | Reads the current state of out0-7 |
+| IN       | 0x8000004 (R) | Reads the current state of in0-7 |
+
+### UART
+
+| Register | Address | Description |
+| -------- | ------- | ----------- |
+| DATA     | 0x8000010 (W) | Transmits the byte |
+| DATA     | 0x8000010 (R) | Reads any received byte |
+| STATUS   | 0x8000014 (R) | Bit 0 indicates whether the UART TX is busy, bytes should not be written to the data register while this bit is set.  Bit 1 indicates whether a received byte is available to be read. |
+
+### SPI
+
+| Register | Address | Description |
+| -------- | ------- | ----------- |
+| DATA     | 0x8000020 (W) | Transmits the byte in bits 7-0, bit 8 is set if this is the last byte of the transaction, bit 9 controls Data/Command on out3 |
+| DATA     | 0x8000020 (R) | Reads the last received byte |
+| CONFIG   | 0x8000024 (W) | The low 2 bits set the clock divisor for the SPI clock to 2*(value + 1) |
+| STATUS   | 0x8000024 (R) | Bit 0 indicates whether the SPI is busy, bytes should not be written or read from the data register while this bit is set. |
+
+# How to test
+
+Load an image into flash and then select the design.
+
+Reset the design as follows:
+
+* Set rst_n high and then low to ensure the design sees a falling edge of rst_n.  The bidirectional IOs are all set to inputs while rst_n is low.
+* Program the flash and leave flash in continuous read mode, and the PSRAMs in QPI mode
+* Drive all the QSPI CS high and set SD2:SD0 to the read latency of the QSPI flash and PSRAM in cycles.
+* Clock at least 8 times and stop with clock high
+* Release all the QSPI lines
+* Set rst_n high
+* Set clock low
+* Start clocking normally
+
+Based on the observed latencies from tt3p5 testing, at the target 64MHz clock a read latency of 2 or 3 is likely required.  The maximum supported latency is currently 3, but should get up to 5 to have a chance at running at faster clock speeds.
+
+The above should all be handled by some MicroPython scripts for the RP2040 on the TT demo PC.
+
+Build programs using the riscv32-unknown-elf toolchain and the [tinyQV-sdk](https://github.com/MichaelBell/tinyQV-sdk), some examples are [here](https://github.com/MichaelBell/tinyQV-projects).
+
+# External hardware
+
+The design is intended to be used with this [QSPI PMOD](https://github.com/mole99/qspi-pmod) on the bidirectional PMOD.  This has a 16MB flash and 2 8MB RAMs.
+
+The UART is on the correct pins to be used with the hardware UART on the RP2040 on the demo board.
+
+The SPI controller is intended to make it easy to drive an ST7789 LCD display (more details to be added).
+
+It may be useful to have buttons to use on the GPIO inputs.

projects/tt_um_MichaelBell_tinyQV/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "TinyQV Risc-V SoC"      # Project title
+  author:       "Michael Bell"      # Your name
+  discord:      "rebelmike"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "A Risc-V SoC for Tiny Tapeout"      # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     64000000       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "2x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_MichaelBell_tinyQV"
+
+  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
+  source_files:        
+    - "project.v"
+    - "tinyQV/cpu/tinyqv.v"
+    - "tinyQV/cpu/alu.v"
+    - "tinyQV/cpu/core.v"
+    - "tinyQV/cpu/counter.v"
+    - "tinyQV/cpu/cpu.v"
+    - "tinyQV/cpu/decode.v"
+    - "tinyQV/cpu/mem_ctrl.v"
+    - "tinyQV/cpu/qspi_ctrl.v"
+    - "tinyQV/cpu/register.v"
+    - "tinyQV/peri/uart/uart_tx.v"
+    - "tinyQV/peri/uart/uart_rx.v"
+    - "tinyQV/peri/spi/spi.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: "Interrupt 0"
+  ui[1]: "Interrupt 1"
+  ui[2]: "SPI MISO"
+  ui[3]: "UART RX"
+  ui[4]: "GP in4"
+  ui[5]: "GP in5"
+  ui[6]: "GP in6"
+  ui[7]: "GP in7"
+
+  # Outputs
+  uo[0]: "SPI CS"
+  uo[1]: "SPI SCK"
+  uo[2]: "SPI MOSI"
+  uo[3]: "SPI DC"
+  uo[4]: "UART TX"
+  uo[5]: "UART RTS"
+  uo[6]: "GP out0"
+  uo[7]: "GP out1"
+
+  # Bidirectional pins
+  uio[0]: "Flash CS"
+  uio[1]: "SD0"
+  uio[2]: "SD1"
+  uio[3]: "SCK"
+  uio[4]: "SD2"
+  uio[5]: "SD3"
+  uio[6]: "RAM A CS"
+  uio[7]: "RAM B CS"
+
+# Do not change!
+yaml_version: 6

projects/tt_um_MichaelBell_tinyQV/stats/metrics.csv

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+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_MichaelBell_tinyQV,wokwi,flow completed,0h8m2s0ms,0h6m44s0ms,125498.48081231929,0.0756025088,62749.240406159646,64.51,80.7418,688.31,4003,0,0,0,0,0,0,0,2,2,0,-1,-1,122136,32510,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,80712795.0,0.0,57.56,40.4,18.62,4.12,-1,3938,6502,344,2837,0,0,0,4651,94,1,99,163,846,203,66,847,537,525,28,2393,1037,11,1672,4744,9857,72564.5952,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,11.0,90.9090909090909,10,1,50,153.18,153.6,0.3,1,10,0.72,0,sky130_fd_sc_hd,AREA 0