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{ | ||
"app": "Tiny Tapeout tt06 d9a6d620", | ||
"repo": "https://github.com/wongmatthew73/tt06-mw-pmic", | ||
"commit": "6277930eee30ec5e2a3425fbd0b9afe35b770ae4", | ||
"workflow_url": "https://github.com/wongmatthew73/tt06-mw-pmic/actions/runs/8667425448", | ||
"sort_id": 1713446628760, | ||
"openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3", | ||
"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943" | ||
} |
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<!--- | ||
This file is used to generate your project datasheet. Please fill in the information below and delete any unused | ||
sections. | ||
You can also include images in this folder and reference them in the markdown. Each image must be less than | ||
512 kb in size, and the combined size of all images must be less than 1 MB. | ||
--> | ||
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## How it works | ||
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This uses a set of state machines to generate 2 ADC controlled pwms. | ||
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A heartbeat signal periodically pings the ADC to update the pwm's duty cycle. | ||
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The heartbeat sends the conversion start (convStart) high signal to begin the conversion. The ADC sets up | ||
and then replies with a busy high when the ADC is ready to be read. When the busy high is read, the chip responds with a read and chip select | ||
(rd_cs) which are tied together. The parallel 8bit conversion is sent to the chip. See AD7819YNZ datasheet for details on ADC conversion. The | ||
conversion is Mode 2. | ||
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After the ADC is read, the duel pwms' duty cycles are updated. 0 is the min voltage and 255 is the max voltage. The duel pwms are 180 deg out of | ||
phase and should never overlap. Otherwise this could lead to shoot-thru which could destroy the FETs. A dead zone was built into the state machine | ||
to prevent this overlap. | ||
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## How to use | ||
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After reset, the syncRectifierLs and syncRectifierHs outputs will produce a pwm signal based on the 8bit parallel ADC input. | ||
You need to build the circuit shown in the white paper pdf. You could also just hook up an oscilloscope to | ||
the syncRectifierLs and syncRectifierHs and see the 180 deg out of phase square waves. | ||
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## External hardware | ||
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https://www.analog.com/media/en/technical-documentation/data-sheets/ad7819.pdf (AD7819NZ 8-bit parallel output ADC) | ||
https://www.digikey.com/en/htmldatasheets/production/638815/0/0/1/mcp14700 (MCP14700 Highside Driver) | ||
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## Future Versions | ||
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I plan to build the ADC internally so I'm not tying up 8 GPIO pins with the ADC parallel output. I also would like to implement current sensing, | ||
current feedforward, prebiasing, soft-switching, PID and other more advanced features if I have time. |
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--- | ||
# Tiny Tapeout project information | ||
project: | ||
title: "Power Management IC" | ||
author: "Matthew Wong" | ||
discord: "" | ||
description: "Creates a half bridge PWM duel output from ADC input" | ||
language: "Verilog" | ||
clock_hz: 10000000 | ||
wokwi_id: 0 | ||
|
||
# How many tiles your design occupies? A single tile is about 167x108 uM. | ||
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2 | ||
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||
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||
|
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# Your top module name must start with "tt_um_". Make it unique by including your github username: | ||
top_module: "tt_um_mw73_pmic" | ||
|
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# List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line: | ||
source_files: | ||
- "tt_um_mw73_pmic.v" | ||
- "pmic.v" | ||
- "pwm.v" | ||
- "slow_clk.v" | ||
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# Do not change! | ||
yaml_version: 6 | ||
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documentation: | ||
author: "Matt Wong" | ||
title: "Power Management IC" | ||
language: "Verilog" | ||
description: "Creates a half bridge PWM duel output from ADC input" | ||
|
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# Longer description of how the project works. You can use standard markdown format. | ||
how_it_works: | | ||
This uses a set of state machines to generate 2 ADC controlled pwms. | ||
A heartbeat signal periodically pings the ADC to update the pwm's duty cycle. | ||
The heartbeat sends the conversion start (convStart) high signal to begin the conversion. The ADC sets up | ||
and then replies with a busy high when the ADC is ready to be read. When the busy high is read, the Asic responds with a read and chip select | ||
(rd_cs) which are tied together. When the ADC receives the rd_cs low, the parallel 8bit conversion is sent to the Asic. See AD7819YNZ datasheet | ||
for details on ADC conversion. The conversion is Mode 2. | ||
After the ADC is read, the duel pwms' duty cycles are updated. 0 is the min voltage and 255 is the max voltage. The duel pwms are 180 deg out of | ||
phase and should never overlap. Otherwise this could lead to shoot-thru which could destroy the FETs. A dead zone was built into the state machine | ||
to prevent this overlap. | ||
# Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed | ||
how_to_test: | | ||
After reset, the syncRectifierLs and syncRectifierHs outputs will produce a pwm signal based on the 8bit parallel ADC input. | ||
You need to build the circuit shown in the white paper pdf. See the "doc_link" section below. You could also just hook up an oscilloscope to | ||
the syncRectifierLs and syncRectifierHs and see the 180 deg out of phase square waves. | ||
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. | ||
pinout: | ||
# Inputs | ||
ui[0]: "adcVoltage[0]" | ||
ui[1]: "adcVoltage[1]" | ||
ui[2]: "adcVoltage[2]" | ||
ui[3]: "adcVoltage[3]" | ||
ui[4]: "adcVoltage[4]" | ||
ui[5]: "adcVoltage[5]" | ||
ui[6]: "adcVoltage[6]" | ||
ui[7]: "adcVoltage[7]" | ||
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# Outputs | ||
uo[0]: "convStart" | ||
uo[1]: "rd_cs" | ||
uo[2]: "syncRectifierLs" | ||
uo[3]: "syncRectifierHs" | ||
uo[4]: "" | ||
uo[5]: "" | ||
uo[6]: "" | ||
uo[7]: "" | ||
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# Bidirectional pins | ||
uio[0]: "busy" | ||
uio[1]: "" | ||
uio[2]: "" | ||
uio[3]: "" | ||
uio[4]: "" | ||
uio[5]: "" | ||
uio[6]: "" | ||
uio[7]: "" | ||
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||
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# The following fields are optional | ||
tag: "timer, test" # comma separated list of tags: test, encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator, | ||
external_hw: "AD7819YNZ, MCP1400" # Describe any external hardware needed | ||
discord: "Matt Wong" # Your discord handle, used for communication and automatically assigning tapeout role after a submission | ||
doc_link: "white paper" # URL to longer form documentation, eg the README.md in your repository | ||
clock_hz: 10000000 # Clock frequency in Hz (if required) | ||
picture: "" # relative path to a picture in your repository (must be 512kb or less) |
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY | ||
/work/src,tt_um_mw73_pmic,wokwi,flow completed,0h1m29s0ms,0h1m8s0ms,71401.83751125052,0.01795472,35700.91875562526,44.5,43.3925,532.38,588,0,0,0,0,0,0,0,0,0,0,-1,-1,10472,3854,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,5220355.0,0.0,25.49,18.16,0.49,0.0,-1,1157,1367,42,246,0,0,0,1275,31,50,108,19,222,85,73,123,162,155,10,843,225,0,279,641,1988,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0 |
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