feat: update project tt_um_lisa from kdp1965/tt06-um-lisa

Commit: 40c3ce07917c5c0fc2a289d41dded04534add369
Workflow: https://github.com/kdp1965/tt06-um-lisa/actions/runs/8688772187

projects/tt_um_lisa/LICENSE

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projects/tt_um_lisa/commit_id.json

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+{
+  "app": "Tiny Tapeout tt06 d5153c3f",
+  "repo": "https://github.com/kdp1965/tt06-um-lisa",
+  "commit": "40c3ce07917c5c0fc2a289d41dded04534add369",
+  "workflow_url": "https://github.com/kdp1965/tt06-um-lisa/actions/runs/8688772187",
+  "sort_id": 1713187061806
+}

projects/tt_um_lisa/docs/info.md

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+## How it works
+                                 
+This is a Microprocessor build around an 8-Bit Little ISA (LISA) processor.
+The following is a block diagram of the project:
+
+                                +------+    
+                         +----->|config|   
+                         |      | regs |   
+               |\   +----+----+ +------+  +------+   +------+ 
+    rx1 -----*-| |  |         |           | lisa |   | lisa |
+             | | |  |  Debug  |           | qspi |   | qqspi| QSPI
+    rx2 ---*-|-| +->|  Intf   +---------->|      +<->|      +----> 
+           | | | |  |         |           | QSPI |   | QPSI | CEs
+    rx3 -*-|-|-| |  |         +-------+   | ARB  |   | Ctrl +----> 
+         | | | |/   +---------+  Ctrl |   +--+---+   +------+
+         | | |  |                     |      |                  
+         | | |  |Port                 V      |       +--------+       
+         V V V  |Sel                +-+------+---+   | lisa   |       
+      +---------+-+   +--------+    |            +---+ debug  |       
+      |  debug    |   | HW Int |    |    LISA    |   +--------+       
+      | autobaud  |   |  Mul/  |<-->|    CORE    |   +--------+       
+      |           |   |  Div   |    |            +---+ Periph |    
+      +-----------+   +--------+    +-+-------+--+   |        |    
+                                      |       |      |    gpio+--> 
+                    +-------+   +-----+-+ +---+---+  |     i2c+--> 
+                    | RAM32 +---+ DATA  | | INST  |  |    UART+-> 
+                    | 128B  |   | CACHE | | CACHE |  | timer  |  
+                    +-------+   +-------+ +-------+  +--------+  
+
+   - The LISA Core as a minimal set of register that allow it to run C programs:
+      - Program Counter + Return Address Resister
+      - Stack Pointer and Index Register (Indexed DATA RAM access)
+      - Accumulator
+
+   - Harvard architecture LISA Core (16-bit instruction, 15-bit address space)
+   - Debug interface
+      * UART controlled
+      * Auto detects port from one of 3 interfaces
+      * Auto detects the baud rate
+      * Interfaces with SPI / QSPI SRAM or FLASH
+      * Can erase / program the (Q)SPI FLASH
+      * Read/write LISA core registers
+      * Set LISA breakpoints, single step, etc.
+      * SPI/QSPI programmability (single/quad, port location, CE selects)
+   - (Q)SPI interface for instruction fetch
+   - Onboard 128 Byte RAM for DATA / DATA CACHE
+   - Data bus CACHE controller with 4 32-byte CACHE lines
+   - Instruction CACHE with a single 4-instruction CACHE line
+   - 16-bit programmable timer (with pre-divide)
+   - Debug UART available to LISA core also
+   - 8-bit Input and Output port (PORTA)
+   - 4-bit BIDIR port (PORTB)
+   - I2C Master controller
+   - Hardware 8x8 integer multiplier
+   - Hardware 16/8 divider
+   - Programmable I/O mux for maximum flexibility of I/O usage.
+
+It uses a 32x32 1RW [DFFRAM](https://github.com/AUCOHL/DFFRAM) macro to implement a 128 bytes (1 kilobit) RAM module.
+The 128 Byte ram can be used either as a DATA cache for the processor data bus, giving a 32K Byte address range,
+or the CACHE controller can be disabled, connecting the Lisa processor core to the RAM directly, limiting the 
+data space to 128 bytes.
+
+                                                                                                         
+Reseting the project **does not** reset the RAM contents.
+
+## How to test
+
+You will need to download and compile the C-based assembler, linker and C compiler I wrote (will make available)
+Also need to download the Python based debugger.
+
+  - Assembler is fully functional
+    - Includes limited libraries for crt0, signed int compare, math, etc.
+    - Libraries are still a work in progress
+  - Linker is fully functional
+  - C compiler is functional (no float support at the moment) but is a work in progress.
+  - Python debugger can erase/program the FLASH, program SPI SRAM, start/stop the LISA core, read SRAM and registers.
+

projects/tt_um_lisa/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "LISA SOC (128 bytes)"
+  author:       "Ken Pettit"
+  discord:      "busy_courgette_50064"
+  description:  "8-Bit Microcontroller SOC with 128 bytes DFFRAM module"
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     20000000       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "6x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_lisa"
+
+  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
+  source_files:
+    - "tt_um_lisa.v"
+    - "RAM32.v"
+    - "lisa_core.v"
+    - "lisa_dbg.v"
+    - "lisa_div.v"
+    - "lisa_periph.v"
+    - "lisa_io_mux.v"
+    - "lisa_qqspi.v"
+    - "lisa_qspi_controller.v"
+    - "lisa_rx8n.v"
+    - "lisa_tx8n.v"
+    - "lisa_i2c.v"
+    - "debug_ctrl.v"
+    - "debug_autobaud.v"
+    - "debug_brg.v"
+    - "debug_regs.v"
+    - "data_cache.v"
+    - "inst_cache.v"
+    - "i2c_master_byte_ctrl.v"
+    - "i2c_master_bit_ctrl.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: "pa_in[0]/baud_div[0]"
+  ui[1]: "pa_in[1]/baud_div[1]"
+  ui[2]: "pa_in[2]/baud_div[2]"
+  ui[3]: "pa_in[3]/baud_div[3]/rx"
+  ui[4]: "pa_in[4]/baud_div[4]"
+  ui[5]: "pa_in[5]/baud_div[5]"
+  ui[6]: "pa_in[6]/baud_div[6]"
+  ui[7]: "pa_in[7]/baud_set"
+
+  # Outputs
+  uo[0]: "pa_out[0]"
+  uo[1]: "pa_out[1]"
+  uo[2]: "pa_out[2]"
+  uo[3]: "pa_out[3]"
+  uo[4]: "pa_out[4]/tx"
+  uo[5]: "pa_out[5]"
+  uo[6]: "pa_out[6]"
+  uo[7]: "pa_out[7]/baud_clk"
+
+  # Bidirectional pins
+  uio[0]: "ce0/ce_latch"
+  uio[1]: "mosi/dq1/ce0"
+  uio[2]: "miso/dq2/ce1"
+  uio[3]: "sclk"
+  uio[4]: "rx  /pb_io[0]/scl/sda"
+  uio[5]: "tx  /pb_io[1]/sda/scl"
+  uio[6]: "scl /pb_io[2]/dq2/rx"
+  uio[7]: "sda/pb_io[3]/dq3"
+
+# Do not change!
+yaml_version: 6