Fix AMO problem in verilator

TheSmolBoi · Mar 18, 2019 · a4e49fc · a4e49fc
1 parent 07df142
commit a4e49fc
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Showing 7 changed files with 33 additions and 24 deletions.
diff --git a/CODEOWNERS b/CODEOWNERS
@@ -1 +1,5 @@
+# Global Owners
 *  @zarubaf @msfschaffner
+
+# FPU owners
+src/fpu_wrap.sv @stmach
diff --git a/fpga/src/ariane_xilinx.sv b/fpga/src/ariane_xilinx.sv
@@ -176,6 +176,7 @@ axi_node_wrap_with_slices #(
     // three ports from Ariane (instruction, data and bypass)
     .NB_SLAVE           ( NBSlave                    ),
     .NB_MASTER          ( ariane_soc::NB_PERIPHERALS ),
+    .NB_REGION          ( ariane_soc::NrRegion       ),
     .AXI_ADDR_WIDTH     ( AxiAddrWidth               ),
     .AXI_DATA_WIDTH     ( AxiDataWidth               ),
     .AXI_USER_WIDTH     ( AxiUserWidth               ),
@@ -210,7 +211,7 @@ axi_node_wrap_with_slices #(
         ariane_soc::GPIOBase     + ariane_soc::GPIOLength - 1,
         ariane_soc::DRAMBase     + ariane_soc::DRAMLength - 1
     }),
-    .valid_rule_i ('1)
+    .valid_rule_i (ariane_soc::ValidRule)
 );
 
 // ---------------
@@ -259,7 +260,7 @@ dm_top #(
     .NrHarts          ( 1                 ),
     .BusWidth         ( AxiDataWidth      ),
     .Selectable_Harts ( 1'b1              )
-) i_dm_top ( 
+) i_dm_top (
     .clk_i            ( clk               ),
     .rst_ni           ( rst_n             ), // PoR
     .testmode_i       ( test_en           ),
@@ -305,11 +306,11 @@ axi2mem #(
     .be_o       ( dm_slave_be               ),
     .data_o     ( dm_slave_wdata            ),
     .data_i     ( dm_slave_rdata            )
-);        
+);
 
 axi_master_connect i_dm_axi_master_connect (
-  .axi_req_i(dm_axi_m_req), 
-  .axi_resp_o(dm_axi_m_resp), 
+  .axi_req_i(dm_axi_m_req),
+  .axi_resp_o(dm_axi_m_resp),
   .master(slave[1])
 );
 
@@ -331,8 +332,8 @@ axi_adapter #(
     .valid_o               ( dm_master_r_valid         ),
     .rdata_o               ( dm_master_r_rdata         ),
     .id_o                  (                           ),
-    .critical_word_o       (                           ), 
-    .critical_word_valid_o (                           ), 
+    .critical_word_o       (                           ),
+    .critical_word_valid_o (                           ),
     .axi_req_o             ( dm_axi_m_req              ),
     .axi_resp_i            ( dm_axi_m_resp             )
 );
@@ -521,7 +522,7 @@ AXI_BUS #(
     .AXI_USER_WIDTH ( AxiUserWidth     )
 ) dram();
 
-axi_riscv_atomics #(
+axi_riscv_atomics_wrap #(
     .AXI_ADDR_WIDTH ( AxiAddrWidth     ),
     .AXI_DATA_WIDTH ( AxiDataWidth     ),
     .AXI_ID_WIDTH   ( AxiIdWidthSlaves ),

diff --git a/src/axi_riscv_atomics b/src/axi_riscv_atomics
diff --git a/src/fpu_wrap.sv b/src/fpu_wrap.sv
@@ -362,17 +362,17 @@ generate
           fpu_op_d        = fpnew_pkg::CPKCD;
           fpu_op_mod_d    = fpu_rm_i[0]; // C/D selection from R bit
           vec_replication = 1'b0;        // no replication, R bit used for op
-          fpu_srcfmt_d      = fpnew_pkg::FP64;    // Cast from FP64
+          fpu_srcfmt_d      = fpnew_pkg::FP32;    // Cast from FP32
         end
         // Vectorial Convert-and-Pack from FP64, lower 4 entries
-        VFCPKAB_S : begin
+        VFCPKAB_D : begin
           fpu_op_d        = fpnew_pkg::CPKAB;
           fpu_op_mod_d    = fpu_rm_i[0]; // A/B selection from R bit
           vec_replication = 1'b0;        // no replication, R bit used for op
           fpu_srcfmt_d      = fpnew_pkg::FP64;    // Cast from FP64
         end
         // Vectorial Convert-and-Pack from FP64, upper 4 entries
-        VFCPKCD_S : begin
+        VFCPKCD_D : begin
           fpu_op_d        = fpnew_pkg::CPKCD;
           fpu_op_mod_d    = fpu_rm_i[0]; // C/D selection from R bit
           vec_replication = 1'b0;        // no replication, R bit used for op

diff --git a/src/riscv-dbg b/src/riscv-dbg
diff --git a/tb/ariane_soc_pkg.sv b/tb/ariane_soc_pkg.sv
@@ -57,4 +57,7 @@ package ariane_soc;
         DRAMBase     = 64'h8000_0000
     } soc_bus_start_t;
 
+    localparam NrRegion = 1;
+    localparam logic [NrRegion-1:0][NB_PERIPHERALS-1:0] ValidRule = {{NrRegion * NB_PERIPHERALS}{1'b1}};
+
 endpackage
diff --git a/tb/ariane_testharness.sv b/tb/ariane_testharness.sv
@@ -245,11 +245,11 @@ module ariane_testharness #(
         .be_o       ( dm_slave_be               ),
         .data_o     ( dm_slave_wdata            ),
         .data_i     ( dm_slave_rdata            )
-    );        
+    );
 
     axi_master_connect i_dm_axi_master_connect (
-      .axi_req_i(dm_axi_m_req), 
-      .axi_resp_o(dm_axi_m_resp), 
+      .axi_req_i(dm_axi_m_req),
+      .axi_resp_o(dm_axi_m_resp),
       .master(slave[1])
     );
 
@@ -271,8 +271,8 @@ module ariane_testharness #(
         .valid_o               ( dm_master_r_valid         ),
         .rdata_o               ( dm_master_r_rdata         ),
         .id_o                  (                           ),
-        .critical_word_o       (                           ), 
-        .critical_word_valid_o (                           ), 
+        .critical_word_o       (                           ),
+        .critical_word_valid_o (                           ),
         .axi_req_o             ( dm_axi_m_req              ),
         .axi_resp_i            ( dm_axi_m_resp             )
     );
@@ -326,7 +326,7 @@ module ariane_testharness #(
     logic [AXI_DATA_WIDTH-1:0]    wdata;
     logic [AXI_DATA_WIDTH-1:0]    rdata;
 
-    axi_riscv_atomics #(
+    axi_riscv_atomics_wrap #(
         .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH   ),
         .AXI_DATA_WIDTH ( AXI_DATA_WIDTH      ),
         .AXI_ID_WIDTH   ( AXI_ID_WIDTH_SLAVES ),
@@ -377,6 +377,7 @@ module ariane_testharness #(
     axi_node_intf_wrap #(
         .NB_SLAVE           ( NB_SLAVE                   ),
         .NB_MASTER          ( ariane_soc::NB_PERIPHERALS ),
+        .NB_REGION          ( ariane_soc::NrRegion       ),
         .AXI_ADDR_WIDTH     ( AXI_ADDRESS_WIDTH          ),
         .AXI_DATA_WIDTH     ( AXI_DATA_WIDTH             ),
         .AXI_USER_WIDTH     ( AXI_USER_WIDTH             ),
@@ -411,7 +412,7 @@ module ariane_testharness #(
             ariane_soc::GPIOBase     + ariane_soc::GPIOLength - 1,
             ariane_soc::DRAMBase     + ariane_soc::DRAMLength - 1
         }),
-        .valid_rule_i ('1)
+        .valid_rule_i (ariane_soc::ValidRule)
     );
 
     // ---------------
@@ -440,8 +441,8 @@ module ariane_testharness #(
     );
 
     axi_slave_connect i_axi_slave_connect_clint (
-      .axi_req_o(axi_clint_req), 
-      .axi_resp_i(axi_clint_resp), 
+      .axi_req_o(axi_clint_req),
+      .axi_resp_i(axi_clint_resp),
       .slave(master[ariane_soc::CLINT])
     );
 
@@ -515,8 +516,8 @@ module ariane_testharness #(
     );
 
     axi_master_connect i_axi_master_connect_ariane (
-      .axi_req_i(axi_ariane_req), 
-      .axi_resp_o(axi_ariane_resp), 
+      .axi_req_i(axi_ariane_req),
+      .axi_resp_o(axi_ariane_resp),
       .master(slave[0])
     );
+1 −1		README.md
+316 −243		src/axi_riscv_amos.sv
+338 −17		src/axi_riscv_atomics.sv
+95 −223		src/axi_riscv_atomics_wrap.sv
+206 −131		src/axi_riscv_lrsc.sv
+101 −229		src/axi_riscv_lrsc_wrap.sv
+1 −1		test/axi_riscv_atomics_synth.v
+1 −1		test/axi_riscv_lrsc_synth.v