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1. RISC-V_Core_4_Stage RISC-V_Core_4_Stage Public

   RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set

   8 6

2. OpenSource_Physical_Design OpenSource_Physical_Design Public

   This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

   34 14

3. LowPower LowPower Public

   Various low power labs using sky130

   Verilog 10 4

4. vsdip/vsdsram_sky130 vsdip/vsdsram_sky130 Public

   SourcePawn 39 10

5. vsdsram_caravel vsdsram_caravel Public

   Forked from efabless/caravel_user_project

   https://caravel-user-project.readthedocs.io

   Verilog 2

6. FPGA_Design_Fabric_Architecture FPGA_Design_Fabric_Architecture Public

   This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primarily focused on a complete FPGA flow using the maximum open-s…

   7 5