Project Files

.gitattributes

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+# Auto detect text files and perform LF normalization
+* text=auto
+

LICENSE

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+MIT License
+
+Copyright (c) 2022 GP-2022-Bachelor 
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

README.md

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+# DDR5 PHY Verification
+This repo includes the uvm testbench for the Digital data path of DDR5 phy 
+***************************************************************************
+Files Organization:
+- docs: Verification plan 
+- rtl: The rtl is not included in this project as it is not part of this work
+- scripts: Shell script for test run automation
+- testbench: UVM tb environment (comps, sequences, tests, interfaces, transactions)

run/.fsm.sch.verilog.xml

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+<Command name="schRTLInfo"  delimiter="."  >
+<RTLBlock >
+<RTLInfo   name="state_0"  type="2"  fileName="../rtl/EdgeDetectorFSM.sv"  >
+    <Seg beginLine="29"  endLine="41"  />
+  </RTLInfo>
+<Instance name="top_testbench.ddr_DUT.DM_inst.EdgeDetectorFSM_inst"  />
+</RTLBlock>
+<RTLBlock >
+<RTLInfo   name="current_state_1"  type="2"  fileName="../rtl/CA_Manager.sv"  >
+    <Seg beginLine="41"  endLine="102"  />
+  </RTLInfo>
+<Instance name="top_testbench.ddr_DUT.top_inst.CA_inst"  />
+</RTLBlock>
+<RTLBlock >
+<RTLInfo   name="state_2"  type="2"  fileName="../rtl/GapCounter.sv"  >
+    <Seg beginLine="39"  endLine="49"  />
+  </RTLInfo>
+<Instance name="top_testbench.ddr_DUT.DM_inst.GC_inst"  />
+</RTLBlock>
+<RTLBlock >
+<RTLInfo   name="state_3"  type="2"  fileName="../rtl/generic_FSM.sv"  >
+    <Seg beginLine="19"  endLine="69"  />
+  </RTLInfo>
+<Instance name="top_testbench.ddr_DUT.DM_inst.PD_inst.generic_FSM_inst"  />
+</RTLBlock>
+</Command>

run/Makefile Example

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+# Makefile for UVM Lab6
+
+LD_LIBRARY_PATH = ${NOVAS_HOME}/share/PLI/VCS/LINUX
+
+test = ubus_example_base_test
+env_path = /u/arwaa/PCIe_Training/makefile/sv
+test_path = /u/arwaa/PCIe_Training/makefile/examples
+rtl_path = /u/arwaa/PCIe_Training/makefile/examples/
+
+PROGRAM_TOP = ${test_path}/ubus_tb_top.sv
+TEST_TOP = ${PROGRAM_TOP}
+TOP = ${TEST_TOP}
+DUT = ${rtl_path}dut_dummy.v
+TESTLIST = ubus_example_base_test test_read_modify_write test_r8_w8_r4_w4 test_2m_4s 
+
+log = simv.log
+uvm_ver = uvm-1.1
+seed = 1
+
+compile_switches = -sverilog -lca -debug_access+all -kdb +vcs+vcdpluson -timescale="1ns/100ps" -l ./scratch/comp.log -ntb_opts ${uvm_ver} +incdir+${env_path}+${test_path} ${TOP}
+runtime_switches = -l ${log} +UVM_TESTNAME=${test}
+
+seq = uvm_reg_bit_bash_seq
+
+##### Required to create a make file which contains the following targets
+########## Target to compile the environment
+compile: ${env_path}/*.sv ${TOP}
+ifeq ($(CES64),TRUE)
+	vcs -full64 ${compile_switches}
+	@echo "Compiled in 64-bit mode"
+else
+	vcs ${compile_switches}
+	@echo "Compiled in 32-bit mode"
+endif
+
+########## Target to launch a single test 
+run:
+	simv +ntb_random_seed=${seed} ${runtime_switches} +seq=${seq}
+
+random: simv
+	simv +ntb_random_seed_automatic ${runtime_switches} +seq=${seq}
+
+########## Target to launch all tests 
+run_all:
+	for test in ${TESTLIST} ; do \
+    		simv +ntb_random_seed=${seed} -cm_dir ./scratch/$$test -l ./scratch/$$test/$$test.log +UVM_TESTNAME=$$test +seq=${seq} ; \
+	done
+random_all:
+	for test in ${TESTLIST} ; do \
+    		simv +ntb_random_seed_automatic -cm_dir ./scratch/$$test -l ./scratch/$$test/$$test.log +UVM_TESTNAME=$$test +seq=${seq} ; \
+	done
+
+########## Target to compile and run the simulation
+all: simv run
+
+########## Target to merge coverage database and generate coverage report
+cover:
+	urg -dir ./scratch/*.vdb
+	urg -dir ./scratch/*.vdb -format text
+
+########## Target to clean your workspace before the build 
+clean:
+	rm -rf simv* csrc* *.tmp *.vpd *.key log *.h temp *.log .vcs* *.txt DVE* *.hvp urg* .inter.vpd.uvm .restart* .synopsys* novas.* *.dat *.fsdb verdi* work* vlog*
+
+########## Target for the makefile help
+help:
+	@echo ============================================================================
+	@echo  " 								         "
+	@echo  " USAGE: make target <seed=xxx> <verbosity=YYY> <test=ZZZ>                "
+	@echo  " 								         "
+	@echo  "  xxx is the random seed.  Can be any integer except 0. Defaults to 1    "
+	@echo  "  YYY sets the verbosity filter.  Defaults to UVM_MEDIUM                 "
+	@echo  "  ZZZ selects the uvm test.       Defaults to test_base                  "
+	@echo  " 								         "
+	@echo  " ------------------------- Test TARGETS -------------------------------- "
+	@echo  " all             => Compile TB and DUT files and run the simulation      "
+	@echo  " compile         => Compile TB and DUT files                             "
+	@echo  " run             => Run the simulation with seed                         "
+	@echo  " random          => Run the simulation with random seed                  "
+	@echo  " run_all         => Run the simulation with seed for all the tests       "
+	@echo  " random_all      => Run the simulation with random seed for all the test "
+	@echo  " cover           => Merge coverage database and generate coverage report "
+	@echo  "                                                                         "
+	@echo  " -------------------- ADMINISTRATIVE TARGETS --------------------------- "
+	@echo  " help       => Displays this message                                     "
+	@echo  " clean      => Remove all intermediate simv and log files                "
+	@echo  "								         "
+	@echo  " ---------------------- EMBEDDED SETTINGS ------------------------------ "
+	@echo  " -timescale=\"1ns/100ps\"                                                "
+	@echo  " -debug_all                                                              "
+	@echo ============================================================================