os/arch/arm/src/amebasmart: Fix UART data loss when wakeup from PG

Issue is encountered where bytes are lost on UART wakeup source during resume from sleep

Test Requirements:
Please ensure PR #6482 is applied before testing

Analysis:
- UART FIFO is started but not drained during resume. When the peripheral is initialized again, it causes the FIFO to also be cleared and cause data loss
- Similarly if more than 64 bytes is passed in together, since there is no mechanism to drain the FIFO into RAM it will cause LSR overrun error

This fix drains the FIFO first at KM4, then again at CA32 until it fully wake, then normal Tizen ISR handler resume operation
- The drained buffer is also passed to application layer
- Watchdog is used to monitor UART1 until the FIFO is completely drained