ReadWritableAddressSpace helper

sw/warpshell/src/modules/axi_firewall.rs

@@ -1,31 +1,59 @@
-use super::io::ReadWritable;
+use super::io::{ReadWritable, ReadWritableAddressSpace, Readable, Writable};
 
 pub struct AxiFirewall<'a> {
-    pub ctrl_baseaddr: u64,
-    pub ctrl_channel: &'a dyn ReadWritable
+    pub ctrl: ReadWritableAddressSpace<'a>,
 }
 
+// -- REGISTER MAP ----------------------------------------------------------------------------------------------------
 const MI_SIDE_FAULT_STATUS_REGISTER_OFFSET: u64 = 0x0;
 const MI_SIDE_SOFT_FAULT_CONTROL_REGISTER_OFFSET: u64 = 0x4;
 const MI_SIDE_UNBLOCK_CONTROL_REGISTER_OFFSET: u64 = 0x8;
 const IP_VERSION_REGISTER_OFFSET: u64 = 0x10;
 // const SOFT_PAUSE_REGISTER_OFFSET: u64 = 0x14;
+// --------------------------------------------------------------------------------------------------------------------
 
 impl<'a> AxiFirewall<'a> {
-    pub fn get_ip_version(&self) -> u32 {
-        self.ctrl_channel.read_u32(self.ctrl_baseaddr + IP_VERSION_REGISTER_OFFSET).unwrap()
+    pub fn new(ctrl_channel: &'a dyn ReadWritable, ctrl_baseaddr: u64) -> Self {
+        Self {
+            ctrl: ReadWritableAddressSpace {
+                channel: ctrl_channel,
+                baseaddr: ctrl_baseaddr,
+            },
+        }
+    }
+    // -- MI OPS ------------------------------------------------------------------------------------------------------
+    pub fn get_mi_fault_status(&self) -> u32 {
+        self.ctrl.read_u32(MI_SIDE_FAULT_STATUS_REGISTER_OFFSET)
+    }
+
+    pub fn mi_is_blocked(&self) -> bool {
+        self.get_mi_fault_status() != 0
     }
 
-    pub fn get_mi_side_fault_status(&self) -> u32 {
-        self.ctrl_channel.read_u32(self.ctrl_baseaddr + MI_SIDE_FAULT_STATUS_REGISTER_OFFSET).unwrap()
+    pub fn block_mi(&self) {
+        self.ctrl
+            .write_u32(0x0100_0100, MI_SIDE_SOFT_FAULT_CONTROL_REGISTER_OFFSET);
     }
 
-    pub fn block(&self) {
-        self.ctrl_channel.write_u32(0x0100_0100, self.ctrl_baseaddr + MI_SIDE_SOFT_FAULT_CONTROL_REGISTER_OFFSET).unwrap();
+    pub fn unblock_mi(&self) {
+        self.ctrl
+            .write_u32(0x0, MI_SIDE_SOFT_FAULT_CONTROL_REGISTER_OFFSET);
+        self.ctrl
+            .write_u32(0x1, MI_SIDE_UNBLOCK_CONTROL_REGISTER_OFFSET);
+    }
+    // ----------------------------------------------------------------------------------------------------------------
+
+    pub fn get_ip_version(&self) -> u32 {
+        self.ctrl.read_u32(IP_VERSION_REGISTER_OFFSET)
     }
 
-    pub fn unblock(&self) {
-        self.ctrl_channel.write_u32(0x0, self.ctrl_baseaddr + MI_SIDE_SOFT_FAULT_CONTROL_REGISTER_OFFSET).unwrap();
-        self.ctrl_channel.write_u32(0x1, self.ctrl_baseaddr + MI_SIDE_UNBLOCK_CONTROL_REGISTER_OFFSET).unwrap();
+    pub fn print_status(&self) {
+        println!("VERSION: {:?}", self.get_ip_version());
+        let status = self.get_mi_fault_status();
+        let mi_is_blocked = status != 0;
+        println!("MI_IS_BLOCKED: {:?}", mi_is_blocked);
+        if mi_is_blocked {
+            println!("MI_STATUS: {:?}", status);
+        }
     }
 }

sw/warpshell/src/modules/cms.rs

@@ -0,0 +1,77 @@
+use super::io::{ReadWritable, ReadWritableAddressSpace, Readable, Writable};
+
+pub struct Cms<'a> {
+    pub ctrl: ReadWritableAddressSpace<'a>,
+}
+
+// -- REGISTER MAP ----------------------------------------------------------------------------------------------------
+// Alveo Card Management Solution Subsystem v4.0
+
+const O_MB_RESETN_REG: u64 = 0x02_0000;
+const O_HOST_INTC: u64 = 0x02_2000;
+const O_REG_MAP: u64 = 0x02_8000;
+
+const O_REG_MAP_ID: u64 = 0x0000;
+const O_FW_VERSION_REG: u64 = 0x0004;
+const O_STATUS_REG: u64 = 0x0008;
+const O_ERROR_REG: u64 = 0x000c;
+const O_PROFILE_NAME_REG: u64 = 0x0014;
+const O_CONTROL_REG: u64 = 0x0018;
+const O_12V_PEX_MAX_REG: u64 = 0x0020;
+const O_12V_PEX_AVG_REG: u64 = 0x0024;
+const O_12V_PEX_INS_REG: u64 = 0x0028;
+const O_3V3_PEX_MAX_REG: u64 = 0x002c;
+const O_3V3_PEX_AVG_REG: u64 = 0x0030;
+const O_3V3_PEX_INS_REG: u64 = 0x0034;
+const O_3V3_AUX_MAX_REG: u64 = 0x0038;
+const O_3V3_AUX_AVG_REG: u64 = 0x003c;
+const O_3V3_AUX_INS_REG: u64 = 0x0040;
+const O_12V_AUX_MAX_REG: u64 = 0x0044;
+const O_12V_AUX_AVG_REG: u64 = 0x0048;
+const O_12V_AUX_INS_REG: u64 = 0x004c;
+const O_DDR4_VPP_BTM_MAX_REG: u64 = 0x0050;
+const O_DDR4_VPP_BTM_AVG_REG: u64 = 0x0054;
+const O_DDR4_VPP_BTM_INS_REG: u64 = 0x0058;
+const O_SYS_5V5_MAX_REG: u64 = 0x005c;
+const O_SYS_5V5_AVG_REG: u64 = 0x0060;
+const O_SYS_5V5_INS_REG: u64 = 0x0064;
+
+const O_HOST_STATUS2_REG: u64 = 0x030c;
+// --------------------------------------------------------------------------------------------------------------------
+
+impl<'a> Cms<'a> {
+    pub fn new(ctrl_channel: &'a dyn ReadWritable, ctrl_baseaddr: u64) -> Self {
+        Self {
+            ctrl: ReadWritableAddressSpace {
+                channel: ctrl_channel,
+                baseaddr: ctrl_baseaddr,
+            },
+        }
+    }
+
+    pub fn init(&self) {
+        self.ctrl.write_u32(1, O_MB_RESETN_REG);
+        let mut ready = false;
+        while !ready {
+            ready = (self.ctrl.read_u32(O_REG_MAP + O_HOST_STATUS2_REG) & 1) == 1;
+        }
+    }
+
+    pub fn get_reg_map_id(&self) -> u32 {
+        self.ctrl.read_u32(O_REG_MAP + O_REG_MAP_ID)
+    }
+
+    pub fn get_fw_version(&self) -> u32 {
+        self.ctrl.read_u32(O_REG_MAP + O_FW_VERSION_REG)
+    }
+
+    pub fn get_profile_name(&self) -> u32 {
+        self.ctrl.read_u32(O_REG_MAP + O_PROFILE_NAME_REG)
+    }
+
+    pub fn print_info(&self) {
+        println!("REG_MAP_ID: {:#010x}", self.get_reg_map_id());
+        println!("FW_VERSION: {:#010x}", self.get_fw_version());
+        println!("PROFILE_NAME: {:#010x}", self.get_profile_name());
+    }
+}

sw/warpshell/src/modules/hbicap.rs

@@ -0,0 +1,11 @@
+use super::io::{Readable, Writable, ReadWritableAddressSpace, ReadableAddressSpace, WritableAddressSpace};
+
+pub struct HbIcap<'a> {
+    pub ctrl: ReadWritableAddressSpace<'a>,
+    pub read: ReadableAddressSpace<'a>,
+    pub write: WritableAddressSpace<'a>
+}
+
+// -- REGISTER MAP ----------------------------------------------------------------------------------------------------
+
+// --------------------------------------------------------------------------------------------------------------------

sw/warpshell/src/modules/io.rs

@@ -1,70 +1,70 @@
-use std::{fs::File, os::unix::prelude::FileExt};
-use anyhow::Result;
-
 pub trait Readable {
-    fn read(&self, buf: &mut [u8], offset: u64) -> Result<()>;
+    fn read(&self, buf: &mut [u8], offset: u64);
 
-    fn read_u32(&self, offset: u64) -> Result<u32> {
+    fn read_u32(&self, offset: u64) -> u32 {
         let mut buf: [u8; 4] = [0; 4];
-        self.read(&mut buf, offset)?;
-        Ok(u32::from_le_bytes(buf))
+        self.read(&mut buf, offset);
+        u32::from_le_bytes(buf)
     }
 
-    fn read_u64(&self, offset: u64) -> Result<u64> {
+    fn read_u64(&self, offset: u64) -> u64 {
         let mut buf: [u8; 8] = [0; 8];
-        self.read(&mut buf, offset)?;
-        Ok(u64::from_le_bytes(buf))
+        self.read(&mut buf, offset);
+        u64::from_le_bytes(buf)
     }
 }
 
 pub trait Writable {
-    fn write(&self, buf: &[u8], offset: u64) -> Result<()>;
+    fn write(&self, buf: &[u8], offset: u64);
 
-    fn write_u32(&self, data: u32, offset: u64) -> Result<()> {
+    fn write_u32(&self, data: u32, offset: u64) {
         self.write(&data.to_le_bytes(), offset)
     }
 
-    fn write_u64(&self, data: u64, offset: u64) -> Result<()> {
+    fn write_u64(&self, data: u64, offset: u64) {
         self.write(&data.to_le_bytes(), offset)
     }
 }
 
-pub trait ReadWritable: Readable + Writable {}
+pub trait  ReadWritable: Readable + Writable {}
 
-pub struct ReadableCdev {
-    pub cdev: File
+pub struct ReadableAddressSpace<'a> {
+    channel: &'a dyn Readable,
+    baseaddr: u64
 }
 
-pub struct WritableCdev {
-    pub cdev: File
+pub struct WritableAddressSpace<'a> {
+    channel: &'a dyn Writable,
+    baseaddr: u64
 }
 
-pub struct ReadWritableCdev {
-    pub cdev: File
+pub struct ReadWritableAddressSpace<'a> {
+    pub channel: &'a dyn ReadWritable,
+    pub baseaddr: u64
 }
 
-impl Readable for ReadableCdev {
-    fn read(&self, buf: &mut [u8], offset: u64) -> Result<()> {
-        self.cdev.read_exact_at(buf, offset).map_err(anyhow::Error::from)
+impl Readable for ReadableAddressSpace<'_> {
+    fn read(&self, buf: &mut [u8], offset: u64) {
+        self.channel.read(buf, self.baseaddr + offset);
     }
 }
 
-impl Writable for WritableCdev {
-    fn write(&self, buf: &[u8], offset: u64) -> Result<()> {
-        self.cdev.write_all_at(buf, offset).map_err(anyhow::Error::from)
+impl Writable for WritableAddressSpace<'_> {
+    fn write(&self, buf: &[u8], offset: u64) {
+        self.channel.write(buf, self.baseaddr + offset);
     }
 }
 
-impl Readable for ReadWritableCdev {
-    fn read(&self, buf: &mut [u8], offset: u64) -> Result<()> {
-        self.cdev.read_exact_at(buf, offset).map_err(anyhow::Error::from)
+impl Readable for ReadWritableAddressSpace<'_> {
+    fn read(&self, buf: &mut [u8], offset: u64) {
+        self.channel.read(buf, self.baseaddr + offset);
     }
 }
 
-impl Writable for ReadWritableCdev {
-    fn write(&self, buf: &[u8], offset: u64) -> Result<()> {
-        self.cdev.write_all_at(buf, offset).map_err(anyhow::Error::from)
+impl Writable for ReadWritableAddressSpace<'_> {
+    fn write(&self, buf: &[u8], offset: u64) {
+        self.channel.write(buf, self.baseaddr + offset);
     }
 }
 
-impl ReadWritable for ReadWritableCdev {}
+impl ReadWritable for ReadWritableAddressSpace<'_> {}

sw/warpshell/src/modules/mod.rs

@@ -1,3 +1,5 @@
 pub mod io;
 pub mod xdma;
+pub mod cms;
+pub mod hbicap;
 pub mod axi_firewall;