Alveo U250 support

Makefile

@@ -1,7 +1,10 @@
+# Supported boards and targets:
+#   xilinx_u55n [xdma_gen3x8 xdma_gen4x4]
+#   xilinx_u250 [xdma_gen3x8]
+#   sqrl_cle215 [xdma_gen2x4]
+
 TARGET_BOARD=xilinx_u55n
-TARGET_SHELL=xdma_gen3x8
-# TARGET_BOARD=sqrl_cle215
-# TARGET_SHELL=xdma_gen2x4
+TARGET_SHELL=xdma_gen4x4
 
 build_shell:
 	mkdir -p ./build/$(TARGET_BOARD)/$(TARGET_SHELL)/

hw/shells/xilinx_u250/xdma_gen3x8/build.tcl

@@ -0,0 +1,42 @@
+set script_path [file dirname [file normalize [info script]]]
+
+create_project -part xcu250-figd2104-2-e synth synth
+set_property source_mgmt_mode All [current_project]
+
+# -- [READ FILES] -------------------------------------------------------------
+import_files ${script_path}/shell.bd
+import_files ${script_path}/user.bd
+import_files "${script_path}/io.xdc"
+import_files "${script_path}/misc.xdc"
+import_files "${script_path}/floorplan.xdc"
+import_files "${script_path}/top.v"
+# -----------------------------------------------------------------------------
+
+# -- [GENERATE BDS] -----------------------------------------------------------
+set_property synth_checkpoint_mode Hierarchical [get_files shell.bd]
+set_property synth_checkpoint_mode Hierarchical [get_files user.bd]
+generate_target all [get_files shell.bd]
+generate_target all [get_files user.bd]
+# -----------------------------------------------------------------------------
+
+# -- [COMPILE] ----------------------------------------------------------------
+export_ip_user_files -of_objects [get_files shell.bd] -no_script -sync -force -quiet
+export_ip_user_files -of_objects [get_files user.bd] -no_script -sync -force -quiet
+create_ip_run [get_files -of_objects [get_fileset sources_1] shell.bd]
+create_ip_run [get_files -of_objects [get_fileset sources_1] user.bd]
+
+launch_runs synth_1 -jobs 16
+wait_on_runs synth_1
+
+open_run synth_1
+write_checkpoint -force ./post_synth_xilinx_u250_xdma_gen3x8.dcp
+opt_design -directive Explore
+place_design -directive Auto_1
+phys_opt_design -directive ExploreWithAggressiveHoldFix
+route_design -directive AggressiveExplore
+phys_opt_design -directive ExploreWithAggressiveHoldFix
+write_checkpoint ./post_route_xilinx_u250_xdma_gen3x8.dcp
+write_bitstream -bin_file -force ./warpshell_xilinx_u250_xdma_gen3x8.bit
+write_abstract_shell -cell user_partition -force ./abstract_warpshell_xilinx_u250_xdma_gen3x8.dcp
+write_cfgmem -force -format mcs -interface spix4 -size 128 -loadbit "up 0x01002000 warpshell_xilinx_u250_xdma_gen3x8.bit" -file "warpshell_xilinx_u250_xdma_gen3x8.mcs"
+# -----------------------------------------------------------------------------

hw/shells/xilinx_u250/xdma_gen3x8/edit.tcl

@@ -0,0 +1,21 @@
+set script_path [file dirname [file normalize [info script]]]
+
+create_project -in_memory -part xcu250-figd2104-2-e
+set_property source_mgmt_mode All [current_project]
+
+proc commit {} {
+    validate_bd_design
+    save_bd_design
+    set bd [current_bd_design]
+    puts "Writing to: $::script_path/${bd}.bd"
+    file copy -force ./${bd}/${bd}.bd $::script_path/
+}
+
+file mkdir ./shell/
+file mkdir ./user/
+file copy ${script_path}/shell.bd ./shell/shell.bd
+file copy ${script_path}/user.bd ./user/user.bd
+read_bd ./shell/shell.bd
+read_bd ./user/user.bd
+
+start_gui

hw/shells/xilinx_u250/xdma_gen3x8/floorplan.xdc

@@ -0,0 +1,12 @@
+create_pblock shell_partition
+resize_pblock shell_partition -add {CLOCKREGION_X7Y4:CLOCKREGION_X7Y7}
+add_cells_to_pblock shell_partition [get_cells shell_partition]
+
+create_pblock user_partition
+resize_pblock user_partition -add {CLOCKREGION_X0Y0:CLOCKREGION_X7Y3}
+resize_pblock user_partition -add {CLOCKREGION_X0Y4:CLOCKREGION_X6Y7}
+resize_pblock user_partition -add {CLOCKREGION_X0Y8:CLOCKREGION_X7Y11}
+resize_pblock user_partition -add {CLOCKREGION_X0Y12:CLOCKREGION_X7Y15}
+resize_pblock user_partition -remove {IOB_X0Y217 IOB_X0Y218 IOB_X0Y219 IOB_X0Y220 IOB_X0Y255 IOB_X0Y244 IOB_X0Y245}
+add_cells_to_pblock user_partition [get_cells user_partition]
+set_property HD.RECONFIGURABLE TRUE [get_cells user_partition]

hw/shells/xilinx_u250/xdma_gen3x8/io.xdc

@@ -0,0 +1,55 @@
+# -- [Clocks] ------------------------------------------------------------------
+# pcie refclock
+create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p]
+# ------------------------------------------------------------------------------
+
+# -- [Clock Pins] --------------------------------------------------------------
+set_property PACKAGE_PIN AM10 [get_ports pcie_refclk_clk_n]
+set_property PACKAGE_PIN AM11 [get_ports pcie_refclk_clk_p]
+# ------------------------------------------------------------------------------
+
+# -- [PCIE Pins] ---------------------------------------------------------------
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN BD21} [get_ports pcie_rstn]
+
+set_property PACKAGE_PIN AN8  [get_ports { pcie_mgt_txn[7] }]
+set_property PACKAGE_PIN AN9  [get_ports { pcie_mgt_txp[7] }]
+set_property PACKAGE_PIN AN3  [get_ports { pcie_mgt_rxn[7] }]
+set_property PACKAGE_PIN AN4  [get_ports { pcie_mgt_rxp[7] }]
+set_property PACKAGE_PIN AM6  [get_ports { pcie_mgt_txn[6] }]
+set_property PACKAGE_PIN AM7  [get_ports { pcie_mgt_txp[6] }]
+set_property PACKAGE_PIN AM1  [get_ports { pcie_mgt_rxn[6] }]
+set_property PACKAGE_PIN AM2  [get_ports { pcie_mgt_rxp[6] }]
+set_property PACKAGE_PIN AL8  [get_ports { pcie_mgt_txn[5] }]
+set_property PACKAGE_PIN AL9  [get_ports { pcie_mgt_txp[5] }]
+set_property PACKAGE_PIN AL3  [get_ports { pcie_mgt_rxn[5] }]
+set_property PACKAGE_PIN AL4  [get_ports { pcie_mgt_rxp[5] }]
+set_property PACKAGE_PIN AK6  [get_ports { pcie_mgt_txn[4] }]
+set_property PACKAGE_PIN AK7  [get_ports { pcie_mgt_txp[4] }]
+set_property PACKAGE_PIN AK1  [get_ports { pcie_mgt_rxn[4] }]
+set_property PACKAGE_PIN AK2  [get_ports { pcie_mgt_rxp[4] }]
+set_property PACKAGE_PIN AJ8  [get_ports { pcie_mgt_txn[3] }]
+set_property PACKAGE_PIN AJ9  [get_ports { pcie_mgt_txp[3] }]
+set_property PACKAGE_PIN AJ3  [get_ports { pcie_mgt_rxn[3] }]
+set_property PACKAGE_PIN AJ4  [get_ports { pcie_mgt_rxp[3] }]
+set_property PACKAGE_PIN AH6  [get_ports { pcie_mgt_txn[2] }]
+set_property PACKAGE_PIN AH7  [get_ports { pcie_mgt_txp[2] }]
+set_property PACKAGE_PIN AH1  [get_ports { pcie_mgt_rxn[2] }]
+set_property PACKAGE_PIN AH2  [get_ports { pcie_mgt_rxp[2] }]
+set_property PACKAGE_PIN AG8  [get_ports { pcie_mgt_txn[1] }]
+set_property PACKAGE_PIN AG9  [get_ports { pcie_mgt_txp[1] }]
+set_property PACKAGE_PIN AG3  [get_ports { pcie_mgt_rxn[1] }]
+set_property PACKAGE_PIN AG4  [get_ports { pcie_mgt_rxp[1] }]
+set_property PACKAGE_PIN AF6  [get_ports { pcie_mgt_txn[0] }]
+set_property PACKAGE_PIN AF7  [get_ports { pcie_mgt_txp[0] }]
+set_property PACKAGE_PIN AF1  [get_ports { pcie_mgt_rxn[0] }]
+set_property PACKAGE_PIN AF2  [get_ports { pcie_mgt_rxp[0] }]
+# ------------------------------------------------------------------------------
+
+# -- [Satellite Controller Pins] -----------------------------------------------
+set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN AN21 } [get_ports { satellite_gpio[3] }]
+set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN AM21 } [get_ports { satellite_gpio[2] }]
+set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN AM20 } [get_ports { satellite_gpio[1] }]
+set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN AR20 } [get_ports { satellite_gpio[0] }]
+set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN BA19 } [get_ports satellite_uart_rxd]
+set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN BB19 } [get_ports satellite_uart_txd]
+# ------------------------------------------------------------------------------

hw/shells/xilinx_u250/xdma_gen3x8/misc.xdc

@@ -0,0 +1,12 @@
+# -- [CONFIG] -----------------------------------------------------------------
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
+# -----------------------------------------------------------------------------