Initial U55C support

Quarky93 · Nov 24, 2022 · 2353040 · 2353040
1 parent 2550aad
commit 2353040
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Showing 13 changed files with 1,031 additions and 23 deletions.
diff --git a/Makefile b/Makefile
@@ -1,14 +1,37 @@
+PLATFORM=xilinx_u55n
+
+# -- U55C --
+xilinx_u55c_xdma_gen3x8: ./hw/shells/xilinx_u55c/xdma_gen3x8/*
+	mkdir -p ./build/xilinx_u55c_xdma_gen3x8/
+	cd ./build/xilinx_u55c_xdma_gen3x8/; \
+	vivado -mode batch -source ../../hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl
+
+edit_xilinx_u55c_xdma_gen3x8_shell:
+	rm -rf ./build/edit_xilinx_u55c_xdma_gen3x8/
+	mkdir -p ./build/edit_xilinx_u55c_xdma_gen3x8/
+	cd ./build/edit_xilinx_u55c_xdma_gen3x8/; \
+	vivado -mode batch -source ../../hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl -tclargs shell
+
+edit_xilinx_u55c_xdma_gen3x8_user:
+	rm -rf ./build/edit_xilinx_u55c_xdma_gen3x8/
+	mkdir -p ./build/edit_xilinx_u55c_xdma_gen3x8/
+	cd ./build/edit_xilinx_u55c_xdma_gen3x8/; \
+	vivado -mode batch -source ../../hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl -tclargs user
+
+# -- U55N --
 xilinx_u55n_xdma_gen3x8: ./hw/shells/xilinx_u55n/xdma_gen3x8/*
 	mkdir -p ./build/xilinx_u55n_xdma_gen3x8/
 	cd ./build/xilinx_u55n_xdma_gen3x8/; \
 	vivado -mode batch -source ../../hw/shells/xilinx_u55n/xdma_gen3x8/build.tcl
 
 edit_xilinx_u55n_xdma_gen3x8_shell:
+	rm -rf ./build/edit_xilinx_u55n_xdma_gen3x8/
 	mkdir -p ./build/edit_xilinx_u55n_xdma_gen3x8/
 	cd ./build/edit_xilinx_u55n_xdma_gen3x8/; \
 	vivado -mode batch -source ../../hw/shells/xilinx_u55n/xdma_gen3x8/edit.tcl -tclargs shell
 
 edit_xilinx_u55n_xdma_gen3x8_user:
+	rm -rf ./build/edit_xilinx_u55n_xdma_gen3x8/
 	mkdir -p ./build/edit_xilinx_u55n_xdma_gen3x8/
 	cd ./build/edit_xilinx_u55n_xdma_gen3x8/; \
 	vivado -mode batch -source ../../hw/shells/xilinx_u55n/xdma_gen3x8/edit.tcl -tclargs user

diff --git a/hw/shells/xilinx_u55c/README.md b/hw/shells/xilinx_u55c/README.md
diff --git a/hw/shells/xilinx_u55c/floorplan.xdc b/hw/shells/xilinx_u55c/floorplan.xdc
diff --git a/hw/shells/xilinx_u55c/shell_bd.tcl b/hw/shells/xilinx_u55c/shell_bd.tcl
diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/README.md b/hw/shells/xilinx_u55c/xdma_gen3x8/README.md
@@ -0,0 +1 @@
+# Xilinx U55C XDMA
diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl b/hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl
@@ -0,0 +1,37 @@
+set script_path [file dirname [file normalize [info script]]]
+
+create_project -in_memory -part xcu55c-fsvh2892-2L-e
+set_property source_mgmt_mode All [current_project]
+
+# -- [READ FILES] -------------------------------------------------------------
+source "${script_path}/user.tcl"
+source "${script_path}/shell.tcl"
+read_xdc "${script_path}/io.xdc"
+read_xdc "${script_path}/misc.xdc"
+read_xdc "${script_path}/floorplan.xdc"
+read_verilog "${script_path}/top.v"
+# -----------------------------------------------------------------------------
+
+# -- [CONFIGURE USER BD] ------------------------------------------------------
+cr_bd_user {}
+generate_target all [get_files user.bd]
+# -----------------------------------------------------------------------------
+
+# -- [CONFIGURE SHELL BD] -----------------------------------------------------
+cr_bd_shell {}
+generate_target all [get_files shell.bd]
+# -----------------------------------------------------------------------------
+
+# -- [COMPILE] ----------------------------------------------------------------
+synth_design -top top
+write_checkpoint -force ./post_synth_xilinx_u55n_xdma_gen3x8.dcp
+opt_design -directive Explore
+place_design -directive Auto_1
+phys_opt_design -directive ExploreWithAggressiveHoldFix
+route_design -directive AggressiveExplore
+phys_opt_design -directive ExploreWithAggressiveHoldFix
+write_checkpoint ./post_route_xilinx_u55n_xdma_gen3x8.dcp
+write_bitstream -bin_file -force ./warpshell_xilinx_u55n_xdma_gen3x8.bit
+write_abstract_shell -cell user_partition -force ./abstract_warpshell_xilinx_u55n_xdma_gen3x8.dcp
+write_cfgmem -force -format mcs -interface spix4 -size 128 -loadbit "up 0x01002000 warpshell_xilinx_u55n_xdma_gen3x8.bit" -file "warpshell_xilinx_u55n_xdma_gen3x8.mcs"
+# -----------------------------------------------------------------------------
diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl b/hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl
@@ -0,0 +1,17 @@
+set bd [lindex $argv 0]
+set script_path [file dirname [file normalize [info script]]]
+
+create_project -in_memory -part xcu55c-fsvh2892-2L-e
+set_property source_mgmt_mode All [current_project]
+
+proc commit {} {
+    validate_bd_design
+    puts "Writing to: $::script_path/$::bd.tcl"
+    write_bd_tcl -bd_name $::bd -no_project_wrapper -make_local -force "$::script_path/$::bd.tcl"
+}
+
+source "${script_path}/${bd}.tcl"
+
+start_gui
+
+cr_bd_${bd} {}
diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/floorplan.xdc b/hw/shells/xilinx_u55c/xdma_gen3x8/floorplan.xdc
@@ -0,0 +1,13 @@
+# create_pblock shell_partition
+# resize_pblock shell_partition -add {CLOCKREGION_X7Y1:CLOCKREGION_X7Y5}
+# add_cells_to_pblock shell_partition [get_cells shell_partition]
+# set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {shell_partition/ctrl_firewall shell_partition/dma_firewall}]
+
+# create_pblock user_partition
+# resize_pblock user_partition -add {CLOCKREGION_X0Y4:CLOCKREGION_X6Y7}
+# resize_pblock user_partition -add {CLOCKREGION_X7Y6:CLOCKREGION_X7Y7}
+# resize_pblock user_partition -add {CLOCKREGION_X0Y0:CLOCKREGION_X6Y3}
+# resize_pblock user_partition -add {CLOCKREGION_X7Y0:CLOCKREGION_X7Y0}
+# resize_pblock user_partition -remove {IOB_X0Y103 IOB_X0Y98 IOB_X0Y84 IOB_X0Y93 IOB_X0Y94 IOB_X0Y79 IOB_X0Y78}
+# add_cells_to_pblock user_partition [get_cells user_partition]
+# set_property HD.RECONFIGURABLE TRUE [get_cells user_partition]
diff --git a/hw/shells/xilinx_u55c/io.xdc → hw/shells/xilinx_u55c/xdma_gen3x8/io.xdc b/hw/shells/xilinx_u55c/io.xdc → hw/shells/xilinx_u55c/xdma_gen3x8/io.xdc
@@ -1,20 +1,20 @@
 # -- [Clocks] ------------------------------------------------------------------
-# pcie clock
-create_clock -period 10.000 -name pcie_ref_clk [get_ports pcie_clk_clk_p]
-# sys clock
-create_clock -period 10.000 -name hbm_ref_clk [get_ports hbm_clk_clk_p]
+# pcie refclock
+create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p]
+# hbm refclock
+create_clock -period 10.000 -name sysclk_0 [get_ports sys_refclk_0_clk_p]
 # ------------------------------------------------------------------------------
 
 # -- [Clock Pins] --------------------------------------------------------------
-set_property PACKAGE_PIN AR14 [get_ports pcie_clk_clk_n]
-set_property PACKAGE_PIN AR15 [get_ports pcie_clk_clk_p]
+set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n]
+set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p]
 
-set_property -dict {IOSTANDARD LVDS PACKAGE_PIN BK44} [get_ports hbm_clk_clk_p]
-set_property -dict {IOSTANDARD LVDS PACKAGE_PIN BK43} [get_ports hbm_clk_clk_p]
+set_property -dict {IOSTANDARD LVDS PACKAGE_PIN BK44} [get_ports sys_refclk_0_clk_n]
+set_property -dict {IOSTANDARD LVDS PACKAGE_PIN BK43} [get_ports sys_refclk_0_clk_p]
 # ------------------------------------------------------------------------------
 
 # -- [PCIE Pins] ---------------------------------------------------------------
-set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN BF41} [get_ports pcie_clkreq]
+set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN BF41} [get_ports pcie_rstn]
 
 set_property PACKAGE_PIN AU10 [get_ports { pcie_mgt_txn[7] }]
 set_property PACKAGE_PIN AU11 [get_ports { pcie_mgt_txp[7] }]
@@ -58,16 +58,3 @@ set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN BH46 } [get_ports { satelli
 set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN BJ42 } [get_ports satellite_uart_rxd]
 set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN BH42 } [get_ports satellite_uart_txd]
 # ------------------------------------------------------------------------------
-
-# -- [BITSTREAM] ---------------------------------------------------------------
-set_property CONFIG_VOLTAGE 1.8 [current_design]
-set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
-set_property CONFIG_MODE SPIx4 [current_design]
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design]
-set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
-set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
-set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
-set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
-# ------------------------------------------------------------------------------
diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/misc.xdc b/hw/shells/xilinx_u55c/xdma_gen3x8/misc.xdc
@@ -0,0 +1,12 @@
+# -- [CONFIG] -----------------------------------------------------------------
+set_property CONFIG_VOLTAGE 1.8 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
+# -----------------------------------------------------------------------------