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prepare for tag 1.1 release
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@PulseRainmaker
PulseRainmaker committed Apr 30, 2017
1 parent 5b7c136 commit 471cac1
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Showing 5 changed files with 104 additions and 39 deletions.
2 changes: 1 addition & 1 deletion UART/FP51/Serial_8051.svh
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Expand Up @@ -80,7 +80,7 @@ extern module UART_RX_FIFO #(parameter FIFO_SIZE = 4, WIDTH = 8)(
);

extern module wb_Serial_8051
#(parameter STABLE_TIME, MAX_BAUD_PERIOD, REG_ADDR_SCON, REG_ADDR_SBUF) (
#(parameter STABLE_TIME, MAX_BAUD_PERIOD, REG_ADDR_SCON, REG_ADDR_SBUF, FIFO_SIZE = 4) (

//=======================================================================
// clock / reset
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3 changes: 2 additions & 1 deletion UART/FP51/UART_RX_FIFO.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,8 @@ module UART_RX_FIFO #(parameter FIFO_SIZE = 4, WIDTH = 8)(
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// Signals
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
logic [0 : FIFO_SIZE - 1][WIDTH - 1 : 0] mem /* synthesis ramstyle = "logic" */ ;
logic [0 : FIFO_SIZE - 1][WIDTH - 1 : 0] mem;

logic unsigned [$clog2(FIFO_SIZE) - 1 : 0] write_pointer = 0;
logic unsigned [$clog2(FIFO_SIZE) - 1 : 0] read_pointer = 0;
// wire unsigned [$clog2(FIFO_SIZE) - 1 : 0] next_write_pointer;
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28 changes: 14 additions & 14 deletions UART/FP51/wb_Serial_8051.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@
`default_nettype none

module wb_Serial_8051
#(parameter STABLE_TIME, MAX_BAUD_PERIOD, REG_ADDR_SCON, REG_ADDR_SBUF) (
#(parameter STABLE_TIME, MAX_BAUD_PERIOD, REG_ADDR_SCON, REG_ADDR_SBUF, FIFO_SIZE = 4) (

//=======================================================================
// clock / reset
Expand Down Expand Up @@ -70,11 +70,11 @@ module wb_Serial_8051
logic unsigned [DATA_WIDTH - 1 : 0] dat_o_mux;

wire unsigned [DATA_WIDTH - 1 : 0] write_addr;
// wire unsigned [DATA_WIDTH - 1 : 0] read_addr;
// wire unsigned [DATA_WIDTH - 1 : 0] read_addr;

logic UART_start_TX;
// logic UART_start_RX;
// logic UART_start_RX;

logic UART_RI_d1, UART_TI_d1;
wire UART_RI, UART_TI;
Expand All @@ -88,7 +88,7 @@ module wb_Serial_8051

wire SCON_SM0, SCON_SM1, SCON_SM2, SCON_REN;
// wire SCON_TB8;
// wire SCON_RB8;
// wire SCON_RB8;



Expand Down Expand Up @@ -155,7 +155,7 @@ module wb_Serial_8051
end : UART_start_RX_proc
*/

/*
/*
always_ff @(posedge clk, negedge reset_n) begin : UART_start_RX_proc
if (!reset_n) begin
UART_start_RX <= 0;
Expand Down Expand Up @@ -198,14 +198,14 @@ module wb_Serial_8051
SCON_d1 <= SCON;
end
end
assign SCON_SM0 = SCON[7];
assign SCON_SM1 = SCON[6];
assign SCON_SM2 = SCON[5];
assign SCON_REN = SCON[4];
assign SCON_TI = SCON[1];
assign SCON_RI = SCON[0];
assign SCON_SM1 = SCON[6];
assign SCON_SM2 = SCON[5];
assign SCON_REN = SCON[4];
assign SCON_TI = SCON[1];
assign SCON_RI = SCON[0];

//=======================================================================
// UART
Expand Down Expand Up @@ -254,7 +254,7 @@ module wb_Serial_8051
//=======================================================================
assign RI_rising = ((~UART_RI_d1) & UART_RI);

UART_RX_FIFO #(.FIFO_SIZE (4)) uart_rx_fifo_i (.*,
UART_RX_FIFO #(.FIFO_SIZE (FIFO_SIZE)) uart_rx_fifo_i (.*,
.fifo_write (RI_rising),
.fifo_data_in (UART_SBUF_received),

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7 changes: 6 additions & 1 deletion flash_loader/flash_loader.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,8 @@
parameter int FLASH_LOADER_BUF_FILL_BIT_INDEX = 3;
parameter int FLASH_LOADER_SAVE_BEGIN_BIT_INDEX = 4;
parameter int FLASH_LOADER_SAVE_END_BIT_INDEX = 5;
parameter int FLASH_LOADER_FLASH_READ_BIT_INDEX = 6;


parameter int FLASH_LOADER_ONCHIP_FLASH_BITS = 17;
parameter int FLASH_LOADER_SEGMENT_SIZE_BYTES = 2048;
Expand Down Expand Up @@ -77,7 +79,10 @@ extern module wb_flash_loader #(REG_ADDR_DATA0,
output wire done_flag,

output logic ping_busy,
output logic pong_busy
output logic pong_busy,

output logic unsigned [1 : 0] flash_buffer_ping_state_out,
output logic unsigned [1 : 0] flash_buffer_pong_state_out


);
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103 changes: 81 additions & 22 deletions flash_loader/wb_flash_loader.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,11 @@ module wb_flash_loader #(REG_ADDR_DATA0,
output wire done_flag,

output logic ping_busy,
output logic pong_busy
output logic pong_busy,

output logic unsigned [1 : 0] flash_buffer_ping_state_out,
output logic unsigned [1 : 0] flash_buffer_pong_state_out



);
Expand All @@ -83,10 +87,12 @@ module wb_flash_loader #(REG_ADDR_DATA0,

wire unsigned [31 : 0] csr_data;

logic unsigned [31 : 0] csr_read_data_reg;

logic unsigned [31 : 0] read_data_reg;
logic csr0_data1;
logic flash_read;
logic flash_read_d1;

logic unsigned [DATA_WIDTH - 1 : 0] csr_control_reg;
logic unsigned [DATA_WIDTH - 1 : 0] csr_control_reg;
logic csr_read;
logic csr_read_d1;
logic csr_write;
Expand All @@ -97,8 +103,8 @@ module wb_flash_loader #(REG_ADDR_DATA0,
wire data_readdatavalid;

logic we;
// wire re;


// wire re;

logic unsigned [DATA_WIDTH - 1 : 0] write_addr;
wire unsigned [DATA_WIDTH - 1 : 0] read_addr;
Expand Down Expand Up @@ -134,6 +140,7 @@ module wb_flash_loader #(REG_ADDR_DATA0,
logic ctl_flip_active_ping0_pong1;
logic ctl_init_active_ping0_pong1;


logic active_ping0_pong1;
logic unsigned [FLASH_LOADER_BUFFER_BITS - 2 : 0] segment_addr_counter;

Expand All @@ -144,6 +151,9 @@ module wb_flash_loader #(REG_ADDR_DATA0,
logic flash_buffer_enable_out_d1;
logic done;
logic done_reg;
logic data_readdatavalid_reg;
logic unsigned [7 : 0] csr_return;
logic active_flag_reg;

//=======================================================================
// data register / output mux
Expand Down Expand Up @@ -216,9 +226,10 @@ module wb_flash_loader #(REG_ADDR_DATA0,
csr_write <= 0;
buf_fill <= 0;
buf_fill_start <= 0;
flash_save_begin_addr <= 0;
flash_save_end_addr <= 0;
done_reg <= 0;
flash_save_begin_addr <= 0;
flash_save_end_addr <= 0;
flash_read <= 0;
done_reg <= 0;

end else begin
csr_addr <= csr_control_reg [FLASH_LOADER_CSR_ADDR_BIT_INDEX];
Expand All @@ -228,6 +239,7 @@ module wb_flash_loader #(REG_ADDR_DATA0,
buf_fill_start <= buf_fill;
flash_save_begin_addr <= csr_control_reg [FLASH_LOADER_SAVE_BEGIN_BIT_INDEX];
flash_save_end_addr <= csr_control_reg [FLASH_LOADER_SAVE_END_BIT_INDEX];
flash_read <= csr_control_reg [FLASH_LOADER_FLASH_READ_BIT_INDEX];

if (buf_fill) begin
done_reg <= 0;
Expand All @@ -240,13 +252,36 @@ module wb_flash_loader #(REG_ADDR_DATA0,

always_ff @(posedge clk, negedge reset_n) begin : csr_read_data_reg_proc
if (!reset_n) begin
csr_read_d1 <= 0;
csr_read_data_reg <= 0;
csr_read_d1 <= 0;
read_data_reg <= 0;
csr0_data1 <= 0;
flash_read_d1 <= 0;
data_readdatavalid_reg <= 0;

csr_return <= 0;
end else begin

csr_return <= {3'b000, data_readdatavalid_reg, ping_busy, pong_busy, done_flag, active_flag};
csr_read_d1 <= csr_read;

if (csr_read_d1) begin
csr_read_data_reg <= csr_readdata;

flash_read_d1 <= flash_read;

if (flash_read_d1) begin
data_readdatavalid_reg <= 0;
end else if (data_readdatavalid) begin
data_readdatavalid_reg <= 1'b1;
end

if (csr_read) begin
csr0_data1 <= 0;
end else if (flash_read) begin
csr0_data1 <= 1'b1;
end

if ((csr_read_d1) && (csr0_data1 == 0)) begin
read_data_reg <= csr_readdata;
end else if ((csr0_data1) && (data_readdatavalid)) begin
read_data_reg <= data_readdata;
end

end
Expand All @@ -261,19 +296,23 @@ module wb_flash_loader #(REG_ADDR_DATA0,

casex (read_addr) // synthesis parallel_case
REG_ADDR_DATA0 : begin
dat_o_mux = csr_read_data_reg [7 : 0];
dat_o_mux = read_data_reg [7 : 0];
end

REG_ADDR_DATA1 : begin
dat_o_mux = csr_read_data_reg [15 : 8];
dat_o_mux = read_data_reg [15 : 8];
end

REG_ADDR_DATA2 : begin
dat_o_mux = csr_read_data_reg [23 : 16];
dat_o_mux = read_data_reg [23 : 16];
end

REG_ADDR_DATA3 : begin
dat_o_mux = csr_read_data_reg [31 : 24];
dat_o_mux = read_data_reg [31 : 24];
end

REG_ADDR_CSR : begin
dat_o_mux = csr_return;
end

default : begin
Expand All @@ -293,7 +332,7 @@ module wb_flash_loader #(REG_ADDR_DATA0,
.avmm_csr_readdata (csr_readdata),

.avmm_data_addr (onchip_flash_address),
.avmm_data_read (1'b0),
.avmm_data_read (flash_read_d1),
.avmm_data_writedata (flash_data_to_write),
.avmm_data_write (flash_buffer_enable_out_d1),
.avmm_data_readdata (data_readdata),
Expand Down Expand Up @@ -333,6 +372,8 @@ module wb_flash_loader #(REG_ADDR_DATA0,
always_ff @(posedge clk, negedge reset_n) begin : onchip_flash_address_proc
if (!reset_n) begin
onchip_flash_address <= 0;
end else if (flash_read) begin
onchip_flash_address <= {csr_data_reg3, csr_data_reg2, csr_data_reg1, csr_data_reg0};
end else if (ctl_load_onchip_flash_address) begin
onchip_flash_address <= onchip_write_begin_addr;
end else if (ctl_inc_onchip_flash_address) begin
Expand Down Expand Up @@ -361,7 +402,7 @@ module wb_flash_loader #(REG_ADDR_DATA0,
always_ff @(posedge clk, negedge reset_n) begin : flash_buffer_ping_state_proc
if (!reset_n) begin
flash_buffer_ping_state <= 0;
end else if (ctl_clear_ping_state) begin
end else if (ctl_clear_ping_state | buf_fill_start) begin
flash_buffer_ping_state <= FLASH_BUF_IDLE;
end else if (flash_buffer_write_enable && (flash_buffer_write_address == 0)) begin
flash_buffer_ping_state <= FLASH_BUF_BUSY;
Expand All @@ -374,7 +415,7 @@ module wb_flash_loader #(REG_ADDR_DATA0,
always_ff @(posedge clk, negedge reset_n) begin : flash_buffer_pong_state_proc
if (!reset_n) begin
flash_buffer_pong_state <= 0;
end else if (ctl_clear_pong_state) begin
end else if (ctl_clear_pong_state | buf_fill_start) begin
flash_buffer_pong_state <= FLASH_BUF_IDLE;
end else if (flash_buffer_write_enable && (flash_buffer_write_address == (FLASH_LOADER_SEGMENT_SIZE_BYTES / 4))) begin
flash_buffer_pong_state <= FLASH_BUF_BUSY;
Expand All @@ -388,7 +429,15 @@ module wb_flash_loader #(REG_ADDR_DATA0,
if (!reset_n) begin
ping_busy <= 0;
pong_busy <= 0;

flash_buffer_ping_state_out <= 0;
flash_buffer_pong_state_out <= 0;

end else begin

flash_buffer_ping_state_out <= flash_buffer_ping_state;
flash_buffer_pong_state_out <= flash_buffer_pong_state;

if (ctl_set_ping_free) begin
ping_busy <= 0;
end else if (ctl_set_ping_busy) begin
Expand Down Expand Up @@ -436,8 +485,18 @@ module wb_flash_loader #(REG_ADDR_DATA0,
end : segment_buffer_read_proc


assign active_flag = 0;
always_ff @(posedge clk, negedge reset_n) begin : active_flag_proc
if (!reset_n) begin
active_flag_reg <= 0;
end else if (buf_fill_start) begin
active_flag_reg <= 1'b1;
end else if (done) begin
active_flag_reg <= 0;
end
end : active_flag_proc

assign done_flag = done_reg;
assign active_flag = active_flag_reg;

//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// FSM main
Expand Down

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