The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering. This project is developed on Intel's CXL FPGA platform
NeoMem project consists of three submodules: NeoMem_FPGA, linux and experiments. NeoMem_FPGA
contains the FPGA code of NeoProf. The linux
folder contains NeoMem's host-side driver, daemon and user-space interface implementation. You can find some click-to-run scripts in the NeoMem_benchmarking
folder, which helps you reproduce the main results of NeoMem paper.
Here are the hardware and software setups used in NeoMem:
- Supermicro SYS-741GE-TNRT platform
- Intel Agilex-7 I series FPGA Dev Kit @400Mhz
- 32GB DDR5 4800Mhz DRAM x4
- Single Socket Xeon 4th 6430 CPU @ 2.1GHz
- Quartus 22.3 with CXL 1.1 IP
To download this repo, run:
git clone [email protected]:PKUZHOU/NeoMem-MICRO-2024.git
cd NeoMem-MICRO-2024
git submodule update --init
To install the provided linux kernel, run:
cd linux
make -j
make modules_install
make install
Note that we hardcode some address in our driver (in linux/drivers/neoprof/neoprof.c), you may need to change it on your platform.
NEOPROFILER_MMIO_BASE defines the start address of the BAR space of the CXL-enabled FPGA device. To find the address on your platform, run:
lspci -vvv
You can find the address as follows.
CXL_MEM_BASE defines the start memory address of the CXL-enabled FPGA device. To find the address on your platform, run:
cat /proc/iomem
The CXL memory device is detected as a DAX device. You can find the address as follows.
To get the result shown in Fig.11 and Fig.13, run
cd NeoMem_benchmarking
python run_all.py
The experiment result will be stored in output/experiment_output
To get the result shown in Fig.16, run
python run_convergence_curve.py
The experiment result will be stored in output/gups_convergence_analysis
To visualize the experiment result, run
cd NeoMem_benchmarking
python parse_result.py
The result figure will be stored in output/fig_output