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feat(Zawrs): support Zawrs extension #786

Merged
merged 1 commit into from
Jan 21, 2025
Merged

feat(Zawrs): support Zawrs extension #786

merged 1 commit into from
Jan 21, 2025

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Tang-Haojin
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@Tang-Haojin Tang-Haojin commented Jan 20, 2025

This commit implements a basic nop-based Zawrs extension.

  • wrs.sto in this commit acts as a nop instruction.
  • wrs.nto in this commit acts as a nop instruction, except it:
    • raises illegal instruction exception when !isModeM && mstatus.TW=1, or
    • raises virtual instruction exception when privState.V && mstatus.TW=0 && hstatus.VTW=1

Seems that completely raises no exception is also a valid implementation,
but raises an exception can help OS to do scheduling during waiting.

@Tang-Haojin Tang-Haojin merged commit ca3a869 into master Jan 21, 2025
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@Tang-Haojin Tang-Haojin deleted the zawrs branch January 21, 2025 11:00
Tang-Haojin added a commit to OpenXiangShan/ready-to-run that referenced this pull request Jan 21, 2025
* NEMU commit: ca3a86992d84a80130a2cfa2c3ada23011df90ac
* NEMU configs:
    * riscv64-xs-ref_defconfig
    * riscv64-dual-xs-ref_defconfig
    * riscv64-xs-ref-debug_defconfig
    * riscv64-dual-xs-ref-debug_defconfig

Including:
  * feat(cbo): supports cbo instr exception check
  * feat(Zawrs): support Zawrs extension (OpenXiangShan/NEMU#786)

---

* spike commit: a04760733715f708b1053725443cd96319e66cf6
* spike config: CPU=XIANGSHAN, CPU=NUTSHELL
* ubuntu 20.04 clang

Including:
   * fix(blocksz): init cache block size when init DifftestRef (OpenXiangShan/riscv-isa-sim#83)
   * feat(Zawrs): support Zawrs extension (OpenXiangShan/riscv-isa-sim#84)
   * fix(vsatp): fix vsatp.ppn value when write vsatp (OpenXiangShan/riscv-isa-sim#85)
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2 participants