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New tlb #272

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merged 2 commits into from
Jan 21, 2025
Merged

New tlb #272

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01299f4
arch-riscv: change MMU size adapt xs-RTL
jueshiwenli Jan 17, 2025
6ddef9e
arch-riscv: Format parameters
jueshiwenli Jan 20, 2025
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2 changes: 1 addition & 1 deletion src/arch/riscv/RiscvMMU.py
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ class RiscvMMU(BaseMMU):
l2_shared = RiscvTLBL2(entry_type="unified")

itb = RiscvTLB(entry_type="instruction",
next_level=Parent.l2_shared,size=32)
next_level=Parent.l2_shared)
dtb = RiscvTLB(entry_type="data",
next_level=Parent.l2_shared, is_dtlb=True)
pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
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8 changes: 5 additions & 3 deletions src/arch/riscv/RiscvTLB.py
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Expand Up @@ -66,15 +66,17 @@ class RiscvTLB(BaseTLB):
is_stage2 = Param.Bool(False,"the tlb is private l2tlb")
#is_stage2 = Param.Bool(True,"the tlb is private l2tlb")
is_the_sharedL2 = Param.Bool(False,"the tlb is shared l2tlb")
size = Param.Int(64, "TLB size")
size = Param.Int(48, "TLB size")
#size = Param.Int(36, "TLB size")
#l2tlb_l1_size = Param.Int(8, "l2TLB_l1 size")
#l2tlb_l2_size = Param.Int(32, "l2TLB_l2 size")
#l2tlb_l3_size = Param.Int(256, "l2TLB_l3 size")
#l2tlb_sp_size = Param.Int(16, "l2TLB_sp size")
l2tlb_l1_size = Param.Int(16, "l2TLB_l1 size")
l2tlb_l2_size = Param.Int(64, "l2TLB_l2 size")
l2tlb_l3_size = Param.Int(512, "l2TLB_l3 size")
#l2tlb_l2_size = Param.Int(64, "l2TLB_l2 size")
l2tlb_l2_size = Param.Int(16, "l2TLB_l2 size")
#l2tlb_l3_size = Param.Int(512, "l2TLB_l3 size")
l2tlb_l3_size = Param.Int(128, "l2TLB_l3 size")
l2tlb_sp_size = Param.Int(16, "l2TLB_sp size")
l2tlb_line_size = Param.Int(8, "l2TLB_line size")
regulation_num = Param.Int(70000, "train nextline num")
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2 changes: 0 additions & 2 deletions src/arch/riscv/pagetable.hh
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Expand Up @@ -70,8 +70,6 @@ const Addr L2PageStoreTypeNum = 5;

const Addr L2TLB_BLK_OFFSET = 3;
const Addr VADDR_CHOOSE_MASK = 7;
const Addr L2TLB_L2_MASK = 0x1f;
const Addr L2TLB_L3_MASK = 0x7f;
const Addr l2tlbLineSize = 8;

const Addr preHitOnHitLNum = 500;
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20 changes: 11 additions & 9 deletions src/arch/riscv/pagetable_walker.cc
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Expand Up @@ -628,7 +628,7 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
gstage);
} else if (l2_level == 1) {
inl2Entry.index =
(gPaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) & (L2TLB_L2_MASK);
(gPaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) & (walker->tlb->L2TLB_L2_MASK);
walker->tlb->L2TLBInsert(inl2Entry.gpaddr, inl2Entry, l2_level, L_L2L2, l2_i, false,
gstage);
}
Expand Down Expand Up @@ -700,7 +700,7 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write)
inl2Entry.paddr = l2pte.ppn;
inl2Entry.pte = l2pte;
if (l2_level == 0) {
inl2Entry.index = (gPaddr >> (L2TLB_BLK_OFFSET + PageShift)) & L2TLB_L3_MASK;
inl2Entry.index = (gPaddr >> (L2TLB_BLK_OFFSET + PageShift)) & walker->tlb->L2TLB_L3_MASK;
walker->tlb->L2TLBInsert(inl2Entry.gpaddr, inl2Entry, l2_level, L_L2L3, l2_i, false,
gstage);
}
Expand Down Expand Up @@ -917,7 +917,8 @@ Walker::WalkerState::twoStageWalk(PacketPtr &write)
inl2Entry.pte = l2pte;
inl2Entry.paddr = l2pte.ppn;
if (l2_level == 0) {
inl2Entry.index = (gPaddr >> (L2TLB_BLK_OFFSET + PageShift)) & L2TLB_L3_MASK;
inl2Entry.index =
(gPaddr >> (L2TLB_BLK_OFFSET + PageShift)) & walker->tlb->L2TLB_L3_MASK;
walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L3, l2_i, false,
vsstage);
} else if (l2_level == 1) {
Expand Down Expand Up @@ -1019,8 +1020,8 @@ Walker::WalkerState::twoStageWalk(PacketPtr &write)
walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L1, l2_i, false,
vsstage);
} else if (l2_level == 1) {
inl2Entry.index =
(entry.vaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) & (L2TLB_L2_MASK);
inl2Entry.index = (entry.vaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) &
(walker->tlb->L2TLB_L2_MASK);
walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L2, l2_i, false,
vsstage);
}
Expand Down Expand Up @@ -1241,8 +1242,8 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
direct);
}
if (l2_level == 1) {
inl2Entry.index =
(entry.vaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) & (L2TLB_L2_MASK);
inl2Entry.index = (entry.vaddr >> (LEVEL_BITS + PageShift + L2TLB_BLK_OFFSET)) &
(walker->tlb->L2TLB_L2_MASK);
walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L2, l2_i, false,
direct);
}
Expand Down Expand Up @@ -1324,7 +1325,7 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
inl2Entry.paddr = l2pte.ppn;
inl2Entry.pte = l2pte;
if (l2_level == 0) {
inl2Entry.index = (entry.vaddr >> (L2TLB_BLK_OFFSET + PageShift)) & L2TLB_L3_MASK;
inl2Entry.index = (entry.vaddr >> (L2TLB_BLK_OFFSET + PageShift)) & walker->tlb->L2TLB_L3_MASK;
walker->tlb->L2TLBInsert(inl2Entry.vaddr, inl2Entry, l2_level, L_L2L3, l2_i, false, direct);
}

Expand Down Expand Up @@ -1406,7 +1407,8 @@ Walker::WalkerState::stepWalk(PacketPtr &write)
nextlineEntry.paddr = l2pte.ppn;
nextlineEntry.pte = l2pte;
if (nextlineEntry.level == 0) {
nextlineEntry.index = (nextlineEntry.vaddr >> (PageShift + L2TLB_BLK_OFFSET)) & (L2TLB_L3_MASK);
nextlineEntry.index =
(nextlineEntry.vaddr >> (PageShift + L2TLB_BLK_OFFSET)) & (walker->tlb->L2TLB_L3_MASK);
walker->tlb->L2TLBInsert(nextlineEntry.vaddr, nextlineEntry, nextlineLevel, L_L2L3, n_l2_i, false,
direct);
} else if (nextlineEntry.level == 1) {
Expand Down
3 changes: 3 additions & 0 deletions src/arch/riscv/tlb.cc
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Expand Up @@ -82,6 +82,7 @@ TLB::TLB(const Params &p) :
l2TlbL1Size(p.l2tlb_l1_size),
l2TlbL2Size(p.l2tlb_l2_size),l2TlbL3Size(p.l2tlb_l3_size),
l2TlbSpSize(p.l2tlb_sp_size),
L2TLB_L2_MASK(0),L2TLB_L3_MASK(0),
regulationNum(p.regulation_num),
tlb(size),lruSeq(0),hitInSp(false),
hitPreEntry(0),hitPreNum(0),
Expand All @@ -101,6 +102,8 @@ TLB::TLB(const Params &p) :
tlbL2L3(l2TlbL3Size *l2tlbLineSize),tlbL2Sp(l2TlbSpSize *l2tlbLineSize),
forwardPre(forwardPreSize),backPre(32)
{
L2TLB_L2_MASK = (((uint64_t)1) << static_cast<int>(std::log2(l2TlbL2Size / 2))) - 1;
L2TLB_L3_MASK = (((uint64_t)1) << static_cast<int>(std::log2(l2TlbL3Size / 4))) - 1;

if (is_L1tlb) {
DPRINTF(TLBVerbose, "tlb11\n");
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6 changes: 6 additions & 0 deletions src/arch/riscv/tlb.hh
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Expand Up @@ -71,6 +71,12 @@ class TLB : public BaseTLB
size_t l2TlbL2Size;
size_t l2TlbL3Size;
size_t l2TlbSpSize;

public:
Addr L2TLB_L2_MASK;
Addr L2TLB_L3_MASK;

protected:
uint64_t regulationNum;
std::vector<TlbEntry> tlb; // our TLB
TlbEntryTrie trie; // for quick access
Expand Down