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arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #164

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Aug 22, 2024
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arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #164

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4 changes: 2 additions & 2 deletions .github/workflows/autotest/gem5.cfg
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Expand Up @@ -14,8 +14,8 @@ log_root = ./log_root
#编译线程
compile_thread = 70
#gcpt路径
gcpt_path = /nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/gcb-restorer.bin
ref_so_path = /nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/nemu-gcbv-ref.so
gcpt_path = /nfs/home/share/gem5_shared_tools/normal-gcb-restorer.bin
ref_so_path = /nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so

set_var = export NEMU_HOME={ref_so_path}

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12 changes: 6 additions & 6 deletions .github/workflows/gem5.yml
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Expand Up @@ -74,8 +74,8 @@ jobs:
run: CC=gcc CXX=g++ scons build/RISCV/gem5.opt --linker=gold -j64
- name: XS-GEM5 - Test xiangshan.py simulation scripts
run: |
export GCBV_REF_SO="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/nemu-gcbv-ref.so"
export GCB_RESTORER="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/gcb-restorer.bin"
export GCBV_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so"
export GCB_RESTORER="/nfs/home/share/gem5_shared_tools/normal-gcb-restorer.bin"
export GEM5_HOME=$(pwd)
mkdir -p $GEM5_HOME/util/xs_scripts/test
cd $GEM5_HOME/util/xs_scripts/test
Expand All @@ -101,8 +101,8 @@ jobs:
run: CC=gcc CXX=g++ scons build/RISCV/gem5.opt --linker=gold -j64
- name: XS-GEM5 - Test xiangshan.py simulation scripts
run: |
export GCBV_REF_SO="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/nemu-gcbv-ref.so"
export GCBV_RESTORER="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/gcbv-restorer.bin"
export GCBV_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so"
export GCBV_RESTORER="/nfs/home/share/gem5_shared_tools/gcbv-restorer.bin"
export GEM5_HOME=$(pwd)
mkdir -p $GEM5_HOME/util/xs_scripts/test_v
cd $GEM5_HOME/util/xs_scripts/test_v
Expand All @@ -120,8 +120,8 @@ jobs:
CC=clang CXX=clang++ scons build/RISCV_CHI/gem5.opt -j 48 --gold-linker
- name: XS-GEM5 - Test xiangshan.py simulation scripts
run: |
export GCBV_MULTI_CORE_REF_SO="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/nemu-gcbv-multi-core-ref.so"
export GCB_MULTI_CORE_RESTORER="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/gcb-2core-restorer.bin"
export GCBV_MULTI_CORE_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-dualcore-nemu-4332a525-so"
export GCB_MULTI_CORE_RESTORER="/nfs/home/share/gem5_shared_tools/gcb-2core-restorer.bin"
export GEM5_HOME=$(pwd)
mkdir -p $GEM5_HOME/util/xs_scripts/test_multi_core
cd $GEM5_HOME/util/xs_scripts/test_multi_core
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8 changes: 4 additions & 4 deletions README.md
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Expand Up @@ -220,10 +220,10 @@ If above branches are not working, you can try the following commits:

| Checkpoint Type | reference design | GCPT restorer
| ---------- | --------- | --------- |
| RV64GCB | NEMU 732e4ccd + riscv64-gem5-ref_defconfig | NEMU 732e4ccd |
| RV64GCBV | NEMU 732e4ccd + riscv64-gem5-ref_defconfig | NEMU b966d274 |
| RV64GCB multi-core | NEMU 732e4ccd + riscv64-gem5-multicore-ref_defconfig | Download Binary from release; Code release soon |
| RV64GCBV multi-core | NEMU 732e4ccd + riscv64-gem5-multicore-ref_defconfig | ~~NOT available yet~~ |
| RV64GCB | NEMU 4332a525 + riscv64-gem5-ref_defconfig | NEMU 732e4ccd |
| RV64GCBV | NEMU 4332a525 + riscv64-gem5-ref_defconfig | NEMU b966d274 |
| RV64GCB multi-core | NEMU 4332a525 + riscv64-gem5-multicore-ref_defconfig | Download Binary from release; Code release soon |
| RV64GCBV multi-core | NEMU 4332a525 + riscv64-gem5-multicore-ref_defconfig | ~~NOT available yet~~ |


**NOTE**:
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1 change: 1 addition & 0 deletions configs/example/fs.py
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Expand Up @@ -484,6 +484,7 @@ def build_drive_system(np):
if args.enable_riscv_vector:
print("Enable riscv vector difftest, need riscv vector-supported gcpt restore and diff-ref-so")
test_sys.enable_riscv_vector = True
test_sys.gcpt_restorer_size_limit = 0x1000
for cpu in test_sys.cpu:
cpu.enable_riscv_vector = True

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20 changes: 2 additions & 18 deletions src/arch/riscv/isa.cc
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Expand Up @@ -257,13 +257,13 @@ void ISA::clear()
std::fill(miscRegFile.begin(), miscRegFile.end(), 0);

miscRegFile[MISCREG_PRV] = PRV_M;
miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x34112D;
miscRegFile[MISCREG_ISA] = 0x800000000034112f;
miscRegFile[MISCREG_VENDORID] = 0;
miscRegFile[MISCREG_ARCHID] = 0;
miscRegFile[MISCREG_IMPID] = 0;
if (FullSystem) {
// Xiangshan assume machine boots with FS off
miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) | (1ULL <<VS_OFFSET);
miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET);
} else {
// SE assumes process starts with FS on
miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
Expand Down Expand Up @@ -516,22 +516,6 @@ ISA::setMiscReg(int misc_reg, RegVal val)
}
break;
case MISCREG_ISA:
{
auto cur_val = readMiscRegNoEffect(misc_reg);
// only allow to disable compressed instructions
// if the following instruction is 4-byte aligned
if ((val & ISA_EXT_C_MASK) == 0 &&
bits(tc->pcState().as<RiscvISA::PCState>().npc(),
2, 0) != 0) {
val |= cur_val & ISA_EXT_C_MASK;
}

if ((val & ISA_EXT_H_MASK) != 0) {
// Do not allow to enable RVH because not implemented yet
val &= ~ISA_EXT_H_MASK;
}
setMiscRegNoEffect(misc_reg, val);
}
break;
case MISCREG_STATUS:
{
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4 changes: 2 additions & 2 deletions util/memory_check/run-xs-with-valgrind.sh
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@@ -1,8 +1,8 @@
set -x

gem5_home=$(pwd)
gcpt_restore_path=/nfs-nvme/home/share/xuyan/shared_payloads/gcpt_restore_checkpoint.bin
ref_so_path=/nfs-nvme/home/share/xuyan/shared_payloads/rvv-nemu-so
gcpt_restore_path=/nfs/home/share/gem5_shared_tools/normal-gcb-restorer.bin
ref_so_path=/nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so
test_cpt=/nfs/home/share/jiaxiaoyu/simpoint_checkpoint_archive/spec06_rv64gcb_O3_20m_gcc12.2.0-intFpcOff-jeMalloc/checkpoint-0-0-0/GemsFDTD/30385/_30385_0.268180_.gz

export NEMU_HOME=$ref_so_path # dummy
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