Merge pull request #4 from rockchip-linux/develop

update

doc/Rockchip_Developer_Guide_MPP_CN.md

@@ -433,6 +433,10 @@ decode函数是decode_put_packet与decode_get_frame数据的结合，为用户
 
 命令参数为RK_U32\*，用于使能H.264解码器的立即输出模式。一旦使能，H.264解码器会忽略丢帧导致的帧序不连续情况，立即输出解码的图像。命令调用时机在decode_put_packet之前。
 
+- MPP_DEC_SET_ENABLE_FAST_PLAY
+
+命令参数为FastPlayMode\*，用于使能H.264解码器的快速起播，不必等到dpb full之后出帧。如果当前帧在I帧之后解码，但在I帧之前显示，可能会出现丢帧的情况。命令调用时机在decode_put_packet之前。
+
 ### 3.2.2 reset
 
 reset接口用于把解码器恢复为正常初始化后的状态。

doc/Rockchip_Developer_Guide_MPP_EN.md

@@ -412,6 +412,10 @@ The command parameter is RK_U32*. It is used to disable error handling of the MP
 
 The command parameter is RK_U32*. It is used to enable the immediate output mode of H.264 decoder. Once enabled the H.264 decoder ignores the frame sequence discontinuity caused by frame dropping or picture order count, just outputs the current decoded image immediately. This command is called before decode_put_packet.
 
+- MPP_DEC_SET_ENABLE_FAST_PLAY
+
+The command parameter is FastPlayMode\*. It is used to enable the fast play of H.264, without waiting for dpb full to output the frame. If the current frame is decoded after the I frame but displayed before the I frame, frame loss may occur. The command is called before decode_put_packet.
+
 ## 3.2.2 reset
 
 The reset interface is used to restore the decoder to the state after normal initialization.

mpp/codec/dec/h264/h264d_api.c

@@ -349,7 +349,9 @@ MPP_RET h264d_init(void *decoder, ParserCfg *init)
     FUN_CHECK(ret = init_vid_ctx(p_Dec->p_Vid));
     FUN_CHECK(ret = init_dec_ctx(p_Dec));
     p_Dec->immediate_out = p_Dec->cfg->base.fast_out;
-    p_Dec->p_Vid->dpb_fast_out = p_Dec->cfg->base.enable_fast_play;
+    mpp_env_get_u32("force_fast_play_mode", &p_Dec->p_Vid->dpb_fast_out,
+                    p_Dec->cfg->base.enable_fast_play);
+    H264D_LOG("fast play mode: %d", p_Dec->p_Vid->dpb_fast_out);
     p_Dec->p_Vid->dpb_first_fast_played = 0;
 __RETURN:
     return ret = MPP_OK;
@@ -447,7 +449,9 @@ MPP_RET h264d_reset(void *decoder)
     p_Dec->dxva_ctx->strm_offset = 0;
     p_Dec->dxva_ctx->slice_count = 0;
     p_Dec->last_frame_slot_idx   = -1;
-    p_Dec->p_Vid->dpb_fast_out = p_Dec->cfg->base.enable_fast_play;
+    mpp_env_get_u32("force_fast_play_mode", &p_Dec->p_Vid->dpb_fast_out,
+                    p_Dec->cfg->base.enable_fast_play);
+    H264D_LOG("fast play mode: %d", p_Dec->p_Vid->dpb_fast_out);
     p_Dec->p_Vid->dpb_first_fast_played = 0;
 
 __RETURN:
@@ -493,6 +497,9 @@ MPP_RET h264d_control(void *decoder, MpiCmd cmd_type, void *param)
     switch (cmd_type) {
     case MPP_DEC_SET_ENABLE_FAST_PLAY:
         p_Dec->p_Vid->dpb_fast_out = (param) ? (*((RK_U32 *)param)) : (1);
+        mpp_env_get_u32("force_fast_play_mode", &p_Dec->p_Vid->dpb_fast_out,
+                        p_Dec->p_Vid->dpb_fast_out);
+        H264D_LOG("fast play mode: %d", p_Dec->p_Vid->dpb_fast_out);
         break;
     case MPP_DEC_SET_MAX_USE_BUFFER_SIZE :
         p_Dec->p_Inp->max_buf_size = (param) ? (*((RK_U32 *)param)) : (0);

mpp/codec/enc/h265/h265e_slice.c

@@ -367,7 +367,7 @@ void h265e_code_slice_header(H265eSlice *slice, MppWriteCtx *bitIf,
     mpp_writer_put_ue(bitIf, slice->m_ppsId);
 
     if (slice_segment_addr != 0) {
-        while (max_ctu_num > (1 << slice_address_addr_bits)) {
+        while (max_ctu_num > (RK_U32)(1 << slice_address_addr_bits)) {
             slice_address_addr_bits++;
         }
         //slice_segment_address

mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c

@@ -2313,11 +2313,11 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task)
 
             if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
                 RK_U32 fbd_offset;
-                RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
-                RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 8);
+                RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
+                RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64);
 
                 regs->ctrl_regs.reg9.fbc_e = 1;
-                regs->av1d_paras.reg68_hor_virstride = w / 64;
+                regs->av1d_paras.reg68_hor_virstride = fbc_hdr_stride / 64;
                 fbd_offset = regs->av1d_paras.reg68_hor_virstride * h * 4;
                 regs->av1d_addrs.reg193_fbc_payload_offset = fbd_offset;
             } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
@@ -2345,7 +2345,7 @@ MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task)
                     ver_virstride = mpp_frame_get_ver_stride(mframe);
                     y_virstride = hor_virstride * ver_virstride;
                     if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
-                        hor_virstride = MPP_ALIGN(mpp_frame_get_width(mframe), 64) / 4;
+                        hor_virstride = mpp_frame_get_fbc_hdr_stride(mframe) / 4;
                     } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
                         hor_virstride = MPP_ALIGN(hor_virstride * 6, 16);
                         y_virstride += y_virstride / 2;

mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c

@@ -380,11 +380,11 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu383Avs2dRegSet *regs, Ha
                         is_fbc, y_virstride, hor_virstride, ver_virstride);
 
         if (is_fbc) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
             RK_U32 fbd_offset;
 
             regs->ctrl_regs.reg9.fbc_e = 1;
-            regs->avs2d_paras.reg68_hor_virstride = pixel_width / 64;
+            regs->avs2d_paras.reg68_hor_virstride = fbc_hdr_stride / 64;
             fbd_offset = regs->avs2d_paras.reg68_hor_virstride * MPP_ALIGN(ver_virstride, 64) * 4;
             regs->avs2d_addrs.reg193_fbc_payload_offset = fbd_offset;
         } else if (is_tile) {
@@ -453,6 +453,21 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu383Avs2dRegSet *regs, Ha
             }
         }
 
+        if (p_hal->syntax.refp.scene_ref_enable && p_hal->syntax.refp.scene_ref_slot_idx >= 0) {
+            MppFrame scene_ref = NULL;
+            RK_S32 slot_idx = p_hal->syntax.refp.scene_ref_slot_idx;
+            RK_S32 replace_idx = p_hal->syntax.refp.scene_ref_replace_pos;
+
+            mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &scene_ref);
+
+            if (scene_ref) {
+                regs->avs2d_addrs.reg170_185_ref_base[replace_idx] = get_frame_fd(p_hal, slot_idx);
+                regs->avs2d_addrs.reg195_210_payload_st_ref_base[replace_idx] = regs->avs2d_addrs.reg170_185_ref_base[replace_idx];
+                mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
+                regs->avs2d_addrs.reg217_232_colmv_ref_base[replace_idx] = mpp_buffer_get_fd(mv_buf->buf[0]);
+            }
+        }
+
         regs->avs2d_addrs.reg169_error_ref_base = regs->avs2d_addrs.reg170_185_ref_base[0];
         regs->avs2d_addrs.reg194_payload_st_error_ref_base = regs->avs2d_addrs.reg195_210_payload_st_ref_base[0];
     }

mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c

@@ -437,13 +437,13 @@ static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu383H264dRegSet *regs, Hal
         uv_virstride = hor_virstride * ver_virstride / 2;
 
         if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
             RK_U32 fbd_offset;
 
-            fbd_offset = pixel_width * MPP_ALIGN(ver_virstride, 64) / 16;
+            fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16;
 
             regs->ctrl_regs.reg9.fbc_e = 1;
-            regs->h264d_paras.reg68_hor_virstride = pixel_width / 64;
+            regs->h264d_paras.reg68_hor_virstride = fbc_hdr_stride / 64;
             regs->h264d_addrs.reg193_fbc_payload_offset = fbd_offset;
         } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
             regs->ctrl_regs.reg9.tile_e = 1;

mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c

@@ -985,12 +985,12 @@ static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal,  HalTaskInfo *syn)
             virstrid_uv = stride_uv * ver_virstride / 2;
         }
         if (MPP_FRAME_FMT_IS_FBC(fmt)) {
-            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
             RK_U32 fbd_offset;
 
             hw_regs->ctrl_regs.reg9.fbc_e = 1;
-            hw_regs->h265d_paras.reg68_hor_virstride = pixel_width / 64;
-            fbd_offset = pixel_width * MPP_ALIGN(ver_virstride, 64) / 16;
+            hw_regs->h265d_paras.reg68_hor_virstride = fbc_hdr_stride / 64;
+            fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16;
             hw_regs->h265d_addrs.reg193_fbc_payload_offset = fbd_offset;
         } else if (MPP_FRAME_FMT_IS_TILE(fmt)) {
             hw_regs->ctrl_regs.reg9.tile_e = 1;

mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c

@@ -13,6 +13,7 @@
 #include "mpp_common.h"
 #include "mpp_buffer_impl.h"
 #include "mpp_bitput.h"
+#include "mpp_compat_impl.h"
 
 #include "hal_vp9d_debug.h"
 #include "hal_vp9d_com.h"
@@ -850,16 +851,16 @@ static MPP_RET hal_vp9d_vdpu383_gen_regs(void *hal, HalTaskInfo *task)
         fbc_en = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
 
         if (fbc_en) {
-            RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
-            RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 8);
+            RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
+            RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64);
             RK_U32 fbd_offset;
 
             vp9_hw_regs->ctrl_regs.reg9.fbc_e = 1;
-            vp9_hw_regs->vp9d_paras.reg68_hor_virstride = w / 64;
+            vp9_hw_regs->vp9d_paras.reg68_hor_virstride = fbc_hdr_stride / 64;
             fbd_offset = vp9_hw_regs->vp9d_paras.reg68_hor_virstride * h * 4;
             vp9_hw_regs->vp9d_addrs.reg193_fbc_payload_offset = fbd_offset;
             /* error stride */
-            vp9_hw_regs->vp9d_paras.reg80_error_ref_hor_virstride = w / 64;
+            vp9_hw_regs->vp9d_paras.reg80_error_ref_hor_virstride = fbc_hdr_stride / 64;
         } else {
             sw_y_hor_virstride = (mpp_align_128_odd_plus_64((pic_param->width * bit_depth) >> 3) >> 4);
             sw_uv_hor_virstride = (mpp_align_128_odd_plus_64((pic_param->width * bit_depth) >> 3) >> 4);
@@ -953,6 +954,8 @@ static MPP_RET hal_vp9d_vdpu383_gen_regs(void *hal, HalTaskInfo *task)
         pic_h[1] = vp9_ver_align(ref_frame_height_y) / 2;
         if (fbc_en) {
             y_hor_virstride = uv_hor_virstride = MPP_ALIGN(ref_frame_width_y, 64) / 64;
+            if (*compat_ext_fbc_hdr_256_odd)
+                y_hor_virstride = uv_hor_virstride = (MPP_ALIGN(ref_frame_width_y, 256) | 256) / 64;
         } else {
             y_hor_virstride = uv_hor_virstride = (mpp_align_128_odd_plus_64((ref_frame_width_y * bit_depth) >> 3) >> 4);
         }

mpp/hal/rkenc/h264e/hal_h264e_vepu541.c

@@ -995,6 +995,7 @@ static MPP_RET setup_vepu541_intra_refresh(Vepu541H264eRegSet *regs, HalH264eVep
     RK_U32 stride_h = MPP_ALIGN(w / 16, 4);
     RK_U32 stride_v = MPP_ALIGN(h / 16, 4);
     RK_U32 i = 0;
+    RK_S32 roi_buf_size;
 
     hal_h264e_dbg_func("enter\n");
 
@@ -1003,11 +1004,12 @@ static MPP_RET setup_vepu541_intra_refresh(Vepu541H264eRegSet *regs, HalH264eVep
         goto RET;
     }
 
-    if (NULL == ctx->roi_buf) {
-        RK_S32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
-
+    roi_buf_size = vepu541_get_roi_buf_size(w, h);
+    if (ctx->roi_buf_size < roi_buf_size) {
         if (NULL == ctx->roi_grp)
             mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
+        if (ctx->roi_buf)
+            mpp_buffer_put(ctx->roi_buf);
 
         mpp_buffer_get(ctx->roi_grp, &ctx->roi_buf, roi_buf_size);
         ctx->roi_buf_size = roi_buf_size;

mpp/hal/rkenc/h264e/hal_h264e_vepu580.c

@@ -1488,7 +1488,7 @@ static MPP_RET setup_vepu580_intra_refresh(HalVepu580RegSet *regs, HalH264eVepu5
     RK_U32 refresh_num = ctx->cfg->rc.refresh_num;
     RK_U32 stride_h = MPP_ALIGN(mb_w, 4);
     RK_U32 stride_v = MPP_ALIGN(mb_h, 4);
-    RK_U32 roi_base_buf_size = stride_h * stride_v * 8;
+    RK_S32 roi_base_buf_size = stride_h * stride_v * 8;
     RK_U32 i = 0;
 
     hal_h264e_dbg_func("enter\n");
@@ -1498,9 +1498,11 @@ static MPP_RET setup_vepu580_intra_refresh(HalVepu580RegSet *regs, HalH264eVepu5
         goto RET;
     }
 
-    if (NULL == ctx->roi_base_cfg_buf) {
+    if (ctx->roi_base_buf_size < roi_base_buf_size) {
         if (NULL == ctx->roi_grp)
             mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
+        if (ctx->roi_base_cfg_buf)
+            mpp_buffer_put(ctx->roi_base_cfg_buf);
         mpp_buffer_get(ctx->roi_grp, &ctx->roi_base_cfg_buf, roi_base_buf_size);
         ctx->roi_base_buf_size = roi_base_buf_size;
     }

mpp/hal/rkenc/h265e/hal_h265e_vepu541.c

@@ -839,6 +839,7 @@ static MPP_RET setup_vepu541_intra_refresh(H265eV541RegSet *regs, H265eV541HalCo
     RK_U32 stride_h = MPP_ALIGN(w / 16, 4);
     RK_U32 stride_v = MPP_ALIGN(h / 16, 4);
     RK_U32 i = 0;
+    RK_U32 roi_buf_size;
 
     hal_h265e_dbg_func("enter\n");
 
@@ -847,17 +848,17 @@ static MPP_RET setup_vepu541_intra_refresh(H265eV541RegSet *regs, H265eV541HalCo
         goto RET;
     }
 
-    if (NULL == ctx->roi_buf) {
-        RK_S32 roi_buf_size = vepu541_get_roi_buf_size(w, h);
-
+    roi_buf_size = vepu541_get_roi_buf_size(w, h);
+    if (ctx->roi_buf_size < roi_buf_size) {
         if (NULL == ctx->roi_grp)
             mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
-
+        if (ctx->roi_buf)
+            mpp_buffer_put(ctx->roi_buf);
+        MPP_FREE(ctx->roi_buf_tmp);
+        ctx->roi_buf_tmp = mpp_calloc_size(Vepu541RoiCfg, roi_buf_size);
         mpp_buffer_get(ctx->roi_grp, &ctx->roi_buf, roi_buf_size);
         ctx->roi_buf_size = roi_buf_size;
     }
-    if (NULL == ctx->roi_buf_tmp)
-        ctx->roi_buf_tmp = (Vepu541RoiCfg *)mpp_malloc(Vepu541RoiCfg, stride_h * stride_v);
 
     mpp_assert(ctx->roi_buf);
     mpp_assert(ctx->roi_buf_tmp);

mpp/hal/rkenc/h265e/hal_h265e_vepu580.c

@@ -1767,10 +1767,9 @@ static MPP_RET setup_intra_refresh(H265eV580HalContext *ctx, RK_U32 refresh_idx)
     RK_U32 h = ctx->cfg->prep.height;
     RK_S32 ctu_w = MPP_ALIGN(w, 64) / 64;
     RK_S32 ctu_h = MPP_ALIGN(h, 64) / 64;
-    RK_U32 roi_base_cfg_buf_size = ctu_w * ctu_h * 64;
+    RK_S32 roi_base_cfg_buf_size = ctu_w * ctu_h * 64;
     MppEncROICfg2 *external_roi_cfg = (MppEncROICfg2 *)frm->roi_data;
     RK_U8 *roi_base_cfg_hw_ptr = NULL;
-    RK_U8 *roi_base_cfg_sw_ptr = NULL;
     RK_S32 roi_base_cfg_buf_fd = 0;
     RefreshArea cur_area;
     RK_S32 j, k;
@@ -1787,9 +1786,13 @@ static MPP_RET setup_intra_refresh(H265eV580HalContext *ctx, RK_U32 refresh_idx)
         roi_base_cfg_hw_ptr = mpp_buffer_get_ptr(external_roi_cfg->base_cfg_buf);
         roi_base_cfg_buf_fd = mpp_buffer_get_fd(external_roi_cfg->base_cfg_buf);
     } else {
-        if (NULL == frm->roi_base_cfg_buf) {
+        if (frm->roi_base_buf_size < roi_base_cfg_buf_size) {
             if (NULL == ctx->roi_grp)
                 mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
+            if (frm->roi_base_cfg_buf)
+                mpp_buffer_put(frm->roi_base_cfg_buf);
+            MPP_FREE(frm->roi_base_cfg_sw_buf);
+            frm->roi_base_cfg_sw_buf = mpp_malloc(RK_U8, roi_base_cfg_buf_size);
             mpp_buffer_get(ctx->roi_grp, &frm->roi_base_cfg_buf, roi_base_cfg_buf_size);
         }
         roi_base_cfg_hw_ptr = mpp_buffer_get_ptr(frm->roi_base_cfg_buf);
@@ -1798,11 +1801,6 @@ static MPP_RET setup_intra_refresh(H265eV580HalContext *ctx, RK_U32 refresh_idx)
 
     frm->roi_base_buf_size = roi_base_cfg_buf_size;
 
-    if (NULL == frm->roi_base_cfg_sw_buf) {
-        frm->roi_base_cfg_sw_buf = mpp_malloc(RK_U8, roi_base_cfg_buf_size);
-    }
-    roi_base_cfg_sw_ptr = frm->roi_base_cfg_sw_buf;
-
     memset(frm->roi_base_cfg_sw_buf, 0, roi_base_cfg_buf_size);
 
     if (MPP_OK != cal_refresh_area(ctu_w, ctu_h, refresh_idx, ctx->cfg->rc.refresh_mode, ctx->cfg->rc.refresh_num, &cur_area)) {
@@ -1811,7 +1809,7 @@ static MPP_RET setup_intra_refresh(H265eV580HalContext *ctx, RK_U32 refresh_idx)
         goto __RET;
     }
 
-    RK_U8 *ptr = roi_base_cfg_sw_ptr;
+    RK_U8 *ptr = frm->roi_base_cfg_sw_buf;
     for (j = 0; j < ctu_h; j++) {
         for (k = 0; k < ctu_w; k++) {
             if (j <= cur_area.roi_ctu_y_end && j >= cur_area.roi_ctu_y_sta &&
@@ -1825,7 +1823,7 @@ static MPP_RET setup_intra_refresh(H265eV580HalContext *ctx, RK_U32 refresh_idx)
         }
     }
 
-    memcpy(roi_base_cfg_hw_ptr, roi_base_cfg_sw_ptr, roi_base_cfg_buf_size);
+    memcpy(roi_base_cfg_hw_ptr, frm->roi_base_cfg_sw_buf, roi_base_cfg_buf_size);
 
     if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW)
         regs->reg_base.reg0220_me_rnge.cme_srch_v = 1;

mpp/vproc/iep2/iep2.c

@@ -216,8 +216,15 @@ static MPP_RET iep2_deinit(IepCtx ictx)
 
     close(ctx->fd);
 
-    mpp_buffer_put(ctx->mv_buf);
-    mpp_buffer_put(ctx->md_buf);
+    if (ctx->mv_buf) {
+        mpp_buffer_put(ctx->mv_buf);
+        ctx->mv_buf = NULL;
+    }
+
+    if (ctx->md_buf) {
+        mpp_buffer_put(ctx->md_buf);
+        ctx->md_buf = NULL;
+    }
 
     if (ctx->memGroup) {
         mpp_buffer_group_put(ctx->memGroup);