SimpleSumeSwitch Architecture (v1.2.1 and Earlier)

This page describes the SimpleSumeSwitch architecture for releases 1.2.1 and earlier.

SimpleSumeSwitch Architecture

The SimpleSumeSwitch is the P4 architecture that is currently defined for the NetFPGA SUME. The architecture description can be found in /opt/Xilinx/SDNet/<version_number>/data/p4include/sume_switch.p4 or wherever you have installed Xilinx SDNet. The architecture consists of a single parser, single match-action pipeline, and single deparser. As shown below:

• sume_metadata: corresponds to the tuser bus in the SUME reference_switch design, it is defined as follows:

  struct sume_metadata_t {
      bit<16> dma_q_size; // measured in 32-byte words
      bit<16> nf3_q_size; // measured in 32-byte words
      bit<16> nf2_q_size; // measured in 32-byte words
      bit<16> nf1_q_size; // measured in 32-byte words
      bit<16> nf0_q_size; // measured in 32-byte words
      bit<8> send_dig_to_cpu; // send digest_data to CPU
      bit<8> drop;
      port_t dst_port; // one-hot encoded: {DMA, NF3, DMA, NF2, DMA, NF1, DMA, NF0}
      port_t src_port; // one-hot encoded: {DMA, NF3, DMA, NF2, DMA, NF1, DMA, NF0}
      bit<16> pkt_len; // (bytes) unsigned int
  }
  

  • pkt_len - the size of the packet (not including the Ethernet preamble or FCS) in bytes.
  • src_port - the port on which the packet arrived. For example, if the packet arrived on port nf1 this field would be set to 0b00000100.
  • dst_port - should be set by the user's P4 program to indicate which port or ports (if any) the packet should be sent out of. For example, to send a packet out of ports nf0 and nf2 this field should be set to 0b00010001.
  • drop - if the least significant bit of this field is set to 1 then the packet will be dropped.
  • send_dig_to_cpu - if the least significant bit of this field is set to 1 the digest data will be sent over DMA to the CPU.
  • _q_size - the size of each output queue, measured in terms of 32-byte words (rounded up). This is the size of the output queues when the packet starts being processed by the P4 program.

• digest_data: the format of this bus is defined by the P4 programmer. The only constraint is that it must be defined to be 80 bits wide. For example, to implement an L2 learning switch the digest_data bus could be configured as follows:

  struct digest_data_t {
      bit<8> src_port;
      bit<48> eth_src_addr;
      bit<24> unused;
  }
  

• user_metadata: the format of this bus is also defined by the P4 programmer. It can be used to pass any additional information from the parser to the M/A pipeline and from the M/A pipeline to the deparser.

• in/out control: these signals are used to add/remove entries from tables and read/write control registers.

The Xilinx P4-SDNet toolchain creates an HDL module, which is then wrapped in a small wrapper and inserted into the NetFPGA SUME reference switch architecture, as indicated by the image below.