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MIPI 2.0 required Tclk-prepare + Tclk-zero must greater than 300 nsec. On Smith, DSI0 Tclk-prepare + Tclk-zero = 282 nsec. As moto force the mipi bit clock rate to 1102MHZ, the mipi timing should be updated too. Update the mipi timing with 1102MHZ. Change-Id: I5d2c03808a065008b28a0f75717598983a4fc49d Signed-off-by: shuoyan <[email protected]> Reviewed-on: https://gerrit.mot.com/1741081 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Ling Jin <[email protected]> Submit-Approved: Jira Key
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shuoyan
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