[DRAM_SUNIV] correct m=m_factor+1 enumerations

[Apaczer]

Holy moly! The uboot upstream code doesn't allow for PLL_DDR outputs with divisors (mostly) other than 1, so 174MHz is not applicable by default (it just reverts to 168).

List with correct values (after change) for ddr_clock:

96,102,104,108,112,114,120,126,128,132,136,138,144,150,152,156,160,162,168,174,176,180,184,186,192,198,200,204,208,216,224,228,232,234,240,248,252,256,264,270,272,276,288,300,

Personally I have found the 198MHz to be max stable and 204 the bleeding edge.

[nfriedly]

Nice work! Is this something that it would make sense to send upstream?

[Apaczer]

Nice work! Is this something that it would make sense to send upstream?

Well that's not the only thing that's missing for e.g.:

diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c
--- a/arch/arm/mach-sunxi/dram_suniv.c
+++ b/arch/arm/mach-sunxi/dram_suniv.c
@@ -57,7 +57,7 @@ struct dram_para

 struct dram_para suniv_dram_para = {
        .size = 32,
+       .clk = 156,
-       .clk = CONFIG_DRAM_CLK,
        .access_mode = 1,
        .cs_num = 1,
        .ddr8_remap = 0,

smbd hardcoded 156MHz from the start (stock frequency), and there may be other parts that has not reach upstream (we're using slightly modded version from https://github.com/aodzip/buildroot-tiny200/blob/master/board/allwinner/suniv-f1c100s/patch/u-boot/0001-v2020.07.11.patch)