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Python2 fixes
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E4ST2W3ST committed Jan 1, 2024
1 parent 3fa96e6 commit 9dc4054
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Showing 2 changed files with 11 additions and 2 deletions.
6 changes: 4 additions & 2 deletions klippy/extras/serial_bridge.py
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,7 @@ def perform_replacement(self, input_string):

for match in hex_matches:
hex_value = match.group(1)
byte_value = bytes.fromhex(hex_value)
byte_value = bytearray.fromhex(hex_value)
replaced_bytes.extend(byte_value)
last_index = match.end()

Expand Down Expand Up @@ -126,7 +126,7 @@ def chunkstring(self, msg, length):
return (msg[0+i:length+i] for i in range(0, len(msg), length))

def send_text(self, msg):
self.send_serial(bytes(msg, encoding='utf-8'))
self.send_serial(msg.encode('utf-8'))

def send_serial(self, msg):
if not self._ready:
Expand Down Expand Up @@ -160,6 +160,8 @@ def build_config(self):
def _handle_serial_bridge_response(self, params):
data = params["text"]

data = bytearray(data)

for callback in self.callbacks:
callback(data)

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7 changes: 7 additions & 0 deletions src/stm32/serial_bridge.c
Original file line number Diff line number Diff line change
Expand Up @@ -147,26 +147,33 @@ void serial_bridge_handle_uart_irq(serial_bridge_config_t* config){
}
}

#if CONFIG_ENABLE_SERIAL_BRIDGE_USART1
void
USART1_serial_bridge_IRQHandler(void)
{
serial_bridge_handle_uart_irq(
serial_bridge_get_active_config_for_usart(USART1));
}
#endif

#if CONFIG_ENABLE_SERIAL_BRIDGE_USART2
void
USART2_serial_bridge_IRQHandler(void)
{
serial_bridge_handle_uart_irq(
serial_bridge_get_active_config_for_usart(USART2));
}
#endif


#if CONFIG_ENABLE_SERIAL_BRIDGE_USART6
void
USART6_serial_bridge_IRQHandler(void)
{
serial_bridge_handle_uart_irq(
serial_bridge_get_active_config_for_usart(USART6));
}
#endif

void
serial_bridge_enable_tx_irq(int8_t usart_index)
Expand Down

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