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KatCe/README.md
  • ๐Ÿ‘‹ Hi, Iโ€™m @KatCe
  • ๐Ÿ‘€ Iโ€™m interested in security, digital design verification and embedded software.
  • ๐ŸŒฑ Iโ€™m currently researching formal verification for detecting hardware security vulnerabilities.
  • ๐Ÿ’ž๏ธ Iโ€™m looking to collaborate on formal verification.
  • ๐Ÿ“ซ How to reach me ... https://www.linkedin.com/in/katharina-ceesay-seitz-ba521087/

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  1. comsec-group/mucfi comsec-group/mucfi Public

    Microarchitectural control flow integrity (๐œ‡CFI) verification checks whether there exists a control or data flow from instruction's operands to the program counter.

    Verilog 7 1

  2. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog

  3. kronos kronos Public

    Forked from SonalPinto/kronos

    Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

    SystemVerilog