chisel refactoring to enable split main <-> test

.github/workflows/scala-unit-test.yml

@@ -5,7 +5,7 @@
 # Xiaoling Yi <[email protected]>
 
 # Run Scala Unit Test
-name: Unit Test
+name: Run Scala Unit Test
 on:
   push:
     branches: ["main"]
@@ -20,6 +20,6 @@ jobs:
     steps:
       - uses: actions/checkout@v2
       - name: Run the unit tests
-        working-directory: util/chiselgen
+        working-directory: hw/chisel
         run: |
           sbt test

hw/chisel/.gitignore

@@ -0,0 +1,7 @@
+generated
+project/*
+!project/plugins.sbt
+!project/build.properties
+target
+test_run_dir
+.bsp

hw/chisel/README.md

@@ -0,0 +1,8 @@
+# SNAX Framework Chisel components
+This directory contains SNAX framework components developed in Chisel. You can find documentation for these modules here:
+
+### Streamer
+[documentation](doc/streamer.md)
+
+### CSR Manager
+TODO

hw/chisel/src/main/scala/snax/csr_manager/CsrManager.scala

@@ -115,15 +115,3 @@ class CsrManager(
   io.csr_config_out.bits <> csr
 
 }
-
-// Scala main function for generating CsrManager system verilog file
-object CsrManager extends App {
-  emitVerilog(
-    new CsrManager(
-      csrManagerTestParameters.csrNum,
-      csrManagerTestParameters.csrAddrWidth,
-      csrManagerTestParameters.csrModuleTagName
-    ),
-    Array("--target-dir", "generated/csr_manager")
-  )
-}

hw/chisel/src/main/scala/snax/streamer/DataMover.scala

@@ -15,7 +15,7 @@ import chisel3.util._
   * @param params
   *   The parameter class contains all the parameters of a data mover module
   */
-class DataMoverIO(params: DataMoverParams = DataMoverParams()) extends Bundle {
+class DataMoverIO(params: DataMoverParams) extends Bundle {
 
   // signals for write request address generation
   val ptr_agu_i = Flipped(Decoupled(UInt(params.addrWidth.W)))
@@ -46,7 +46,7 @@ class DataMoverIO(params: DataMoverParams = DataMoverParams()) extends Bundle {
   *   The parameter class contains all the parameters of a data mover module
   */
 class DataMover(
-    params: DataMoverParams = DataMoverParams(),
+    params: DataMoverParams,
     tagName: String = ""
 ) extends Module
     with RequireAsyncReset {
@@ -222,7 +222,7 @@ class DataMover(
 // classes which extend the DataMover module, but are just
 // set to 0 here for testing purposes.
 class DataMoverTester(
-    params: DataMoverParams = DataMoverParams()
+    params: DataMoverParams
 ) extends DataMover(params) {
 
   for (i <- 0 until params.tcdmPortsNum) {

hw/chisel/src/main/scala/snax/streamer/DataReader.scala

@@ -12,7 +12,7 @@ import chisel3.util._
   *   The parameter class contains all the parameters of a data mover module
   */
 class DataReaderIO(
-    params: DataMoverParams = DataMoverParams()
+    params: DataMoverParams
 ) extends DataMoverIO(params) {
 
   // tcdm response
@@ -40,7 +40,7 @@ class DataReaderIO(
   *   The parameter class contains all the parameters of a data mover module
   */
 class DataReader(
-    params: DataMoverParams = DataMoverParams(),
+    params: DataMoverParams,
     tagName: String = ""
 ) extends DataMover(params, tagName) {
   override val desiredName = tagName + "DataReader"
@@ -135,11 +135,3 @@ class DataReader(
   }
 
 }
-
-// Scala main function for generating system verilog file for the DataReader module
-object DataReader extends App {
-  emitVerilog(
-    new DataReader(DataMoverParams()),
-    Array("--target-dir", "generated/streamer")
-  )
-}

hw/chisel/src/main/scala/snax/streamer/DataWriter.scala

@@ -11,7 +11,7 @@ import chisel3.util._
   *   The parameter class contains all the parameters of a data mover module
   */
 class DataWriterIO(
-    params: DataMoverParams = DataMoverParams()
+    params: DataMoverParams
 ) extends DataMoverIO(params) {
 
   // valid data from the queue
@@ -32,7 +32,7 @@ class DataWriterIO(
   *   The parameter class contains all the parameters of a data mover module
   */
 class DataWriter(
-    params: DataMoverParams = DataMoverParams(),
+    params: DataMoverParams,
     tagName: String = ""
 ) extends DataMover(params) {
   override val desiredName = tagName + "DataWriter"
@@ -62,11 +62,3 @@ class DataWriter(
   io.data_fifo_i.ready := io.ptr_agu_i.ready
 
 }
-
-// Scala main function for generating system verilog file for the DataWriter module
-object DataWriter extends App {
-  emitVerilog(
-    new DataWriter(DataMoverParams()),
-    Array("--target-dir", "generated/streamer")
-  )
-}

hw/chisel/src/main/scala/snax/streamer/FIFO.scala

@@ -5,15 +5,15 @@ import chisel3.util._
 
 // Customized FIFO with an extra almost_full signal.
 // almost_full will be asserted when there is Depth-1 elements in the FIFO
-class FIFOIO(width: Int = FIFOTestParameters.fifoWidth) extends Bundle {
+class FIFOIO(width: Int) extends Bundle {
   val in = Flipped(Decoupled(UInt(width.W)))
   val out = Decoupled(UInt(width.W))
   val almost_full = Output(Bool())
 }
 
 class FIFO(
-    depth: Int = FIFOTestParameters.fifoDepth,
-    width: Int = FIFOTestParameters.fifoWidth,
+    depth: Int,
+    width: Int,
     tagName: String = ""
 ) extends Module
     with RequireAsyncReset {
@@ -32,10 +32,3 @@ class FIFO(
   }
 
 }
-
-object FIFO extends App {
-  emitVerilog(
-    new (FIFO),
-    Array("--target-dir", "generated/streamer")
-  )
-}

hw/chisel/src/main/scala/snax/streamer/Parameters.scala

@@ -26,9 +26,9 @@ trait CommonParams {
   *   The bit width of the address.
   */
 case class TemporalAddrGenUnitParams(
-    loopDim: Int = TemporalAddrGenUnitTestParameters.loopDim,
-    loopBoundWidth: Int = TemporalAddrGenUnitTestParameters.loopBoundWidth,
-    addrWidth: Int = TemporalAddrGenUnitTestParameters.addrWidth
+    loopDim: Int,
+    loopBoundWidth: Int,
+    addrWidth: Int
 )
 
 /** This class represents all the parameters for the Spatial Address Generation
@@ -41,9 +41,9 @@ case class TemporalAddrGenUnitParams(
   *   The bit width of the address.
   */
 case class SpatialAddrGenUnitParams(
-    loopDim: Int = SpatialAddrGenUnitTestParameters.loopDim,
-    loopBounds: Seq[Int] = SpatialAddrGenUnitTestParameters.loopBounds,
-    addrWidth: Int = SpatialAddrGenUnitTestParameters.addrWidth
+    loopDim: Int,
+    loopBounds: Seq[Int],
+    addrWidth: Int
 )
 
 /** This class represents all the parameters for the Data Mover (including Data
@@ -63,11 +63,11 @@ case class SpatialAddrGenUnitParams(
   *   FIFO width
   */
 case class DataMoverParams(
-    tcdmPortsNum: Int = DataMoverTestParameters.tcdmPortsNum,
-    spatialBounds: Seq[Int] = DataMoverTestParameters.spatialBounds,
-    spatialDim: Int = DataMoverTestParameters.spatialDim,
-    elementWidth: Int = DataMoverTestParameters.elementWidth,
-    fifoWidth: Int = DataMoverTestParameters.fifoWidth
+    tcdmPortsNum: Int,
+    spatialBounds: Seq[Int],
+    spatialDim: Int,
+    elementWidth: Int,
+    fifoWidth: Int
 ) extends CommonParams
 
 /** FIFO parameters
@@ -173,15 +173,12 @@ trait HasStreamerInferredParams extends HasStreamerCoreParams {
   *   default value of these parameters is from the StreamerTestConstant object
   */
 case class StreamerParams(
-    temporalAddrGenUnitParams: TemporalAddrGenUnitParams =
-      StreamerTestConstant.temporalAddrGenUnitParams,
-    stationarity: Seq[Int] = StreamerTestConstant.stationarity,
-    dataReaderParams: Seq[DataMoverParams] =
-      StreamerTestConstant.dataReaderParams,
-    dataWriterParams: Seq[DataMoverParams] =
-      StreamerTestConstant.dataWriterParams,
-    fifoReaderParams: Seq[FIFOParams] = StreamerTestConstant.fifoReaderParams,
-    fifoWriterParams: Seq[FIFOParams] = StreamerTestConstant.fifoWriterParams,
-    tagName: String = StreamerTestConstant.tagName
+    temporalAddrGenUnitParams: TemporalAddrGenUnitParams,
+    stationarity: Seq[Int],
+    dataReaderParams: Seq[DataMoverParams],
+    dataWriterParams: Seq[DataMoverParams],
+    fifoReaderParams: Seq[FIFOParams],
+    fifoWriterParams: Seq[FIFOParams],
+    tagName: String = ""
 ) extends HasStreamerCoreParams
     with HasStreamerInferredParams

hw/chisel/src/main/scala/snax/streamer/SpatialAddrGenUnit.scala

@@ -79,7 +79,7 @@ trait WithSpatialLoopIndices {
   *   The bit width of the address.
   */
 class SpatialAddrGenUnit(
-    params: SpatialAddrGenUnitParams = SpatialAddrGenUnitParams(),
+    params: SpatialAddrGenUnitParams,
     tagName: String = ""
 ) extends Module
     with RequireAsyncReset
@@ -157,11 +157,3 @@ class SpatialAddrGenUnit(
   )
 
 }
-
-// Scala main function for generating system verilog file for the SpatialAddrGenUnit module
-object SpatialAddrGenUnit extends App {
-  emitVerilog(
-    new SpatialAddrGenUnit(SpatialAddrGenUnitParams()),
-    Array("--target-dir", "generated/streamer")
-  )
-}

hw/chisel/src/main/scala/snax/streamer/Streamer.scala

@@ -27,7 +27,7 @@ class DataFromAcceleratorX(
 
 // csr related io
 class StreamerCsrIO(
-    params: StreamerParams = StreamerParams()
+    params: StreamerParams
 ) extends Bundle {
 
   // configurations interface for a new data operation
@@ -372,56 +372,3 @@ class Streamer(
   }
 
 }
-
-// Scala main function for generating test streamer system verilog file
-object StreamerTester extends App {
-  emitVerilog(
-    new Streamer(StreamerParams()),
-    Array("--target-dir", "generated/streamer/tester")
-  )
-}
-
-// Scala main function for generating system verilog file for different accelerators
-// including GEMM, Post-processing SIMD and MAC engine
-object GemmStreamer extends App {
-  emitVerilog(
-    new Streamer(
-      StreamerParams(
-        temporalAddrGenUnitParams =
-          GeMMStreamerParameters.temporalAddrGenUnitParams,
-        fifoReaderParams = GeMMStreamerParameters.fifoReaderParams,
-        fifoWriterParams = GeMMStreamerParameters.fifoWriterParams,
-        stationarity = GeMMStreamerParameters.stationarity,
-        dataReaderParams = GeMMStreamerParameters.dataReaderParams,
-        dataWriterParams = GeMMStreamerParameters.dataWriterParams
-      )
-    ),
-    Array("--target-dir", "generated/streamer/gemm")
-  )
-}
-
-object PostProcessingStreamer extends App {
-  emitVerilog(
-    new Streamer(
-      StreamerParams(
-        temporalAddrGenUnitParams =
-          PostProcessingStreamerParameters.temporalAddrGenUnitParams,
-        fifoReaderParams = PostProcessingStreamerParameters.fifoReaderParams,
-        fifoWriterParams = PostProcessingStreamerParameters.fifoWriterParams,
-        stationarity = PostProcessingStreamerParameters.stationarity,
-        dataReaderParams = PostProcessingStreamerParameters.dataReaderParams,
-        dataWriterParams = PostProcessingStreamerParameters.dataWriterParams
-      )
-    ),
-    Array("--target-dir", "generated/streamer/pp")
-  )
-}
-
-object MacStreamer extends App {
-  emitVerilog(
-    new Streamer(
-      StreamerParams()
-    ),
-    Array("--target-dir", "generated/streamer/mac")
-  )
-}