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Add the CsrManager for the Post-Processing SIMD datapath #6

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merged 3 commits into from
Jan 24, 2024

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xiaoling-yi
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@xiaoling-yi xiaoling-yi commented Jan 22, 2024

Add the CsrManager for the Post-Processing SIMD datapath to be compatible with the SNAX CSR interface.

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The CsrManager code is the same as for GEMM and Streamer!

@JosseVanDelm
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@xiaoling-yi maybe dumb comment, but are you also testing for negative input now?

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The CsrManager code is the same as for GEMM and Streamer!

Very Cool! Maybe we should then instead provide this as a scala package that is installable via coursier at some point, instead of copying the source files in all three repos 😉 .

@xiaoling-yi xiaoling-yi changed the title Add simdtop Add the CsrManager for the Post-Processing SIMD datapath Jan 23, 2024
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xiaoling-yi commented Jan 23, 2024

@xiaoling-yi maybe dumb comment, but are you also testing for negative input now?

@JosseVanDelm, no. Just randomly generated data test. There are tests for results going out of the output range so they are clamped accordingly in PEAutoTest. Maybe we can add real TinyML workload data test later.

The CsrManager code is the same as for GEMM and Streamer!

Very Cool! Maybe we should then instead provide this as a scala package that is installable via coursier at some point, instead of copying the source files in all three repos 😉 .

Oh! I also think about this. Let me check how difficult it is!

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Good job! Approve! But please check comments first 👀

val config_valid = WireInit(0.B)

// check if the csr address overflow (access certain csr that doesn't exist)
def startCsrAddr = (csrNum - 1).U

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What happens when it overflows?

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Will throw an error at simulation time.

Comment on lines +108 to +118
// handle read requests: keep sending response data until the request succeeds
when(read_csr) {
io.csr_config_in.rsp.bits.data := csr(io.csr_config_in.req.bits.addr)
io.csr_config_in.rsp.valid := 1.B
}.elsewhen(keep_sending_csr_rsp) {
io.csr_config_in.rsp.bits.data := csr_rsp_data_reg
io.csr_config_in.rsp.valid := 1.B
}.otherwise {
io.csr_config_in.rsp.valid := 0.B
io.csr_config_in.rsp.bits.data := 0.U
}

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Shouldn't the keep_sending_csr_rsp take priority over the read_csr? Because when the keep_sending_csr_rsp is active then it should be the first one to come out right?

What happens when both read_csr and keep_sending_csr_rsp occur? Then the one that takes priority is the newest request? I think it should be the one in the buffered register.

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When keep_sending_csr_rsp, the io.csr_config_in.req.ready is low so read_csr will never be high. But good point!

@@ -14,4 +14,9 @@ object SIMDConstant {

// SIMD parallelism
def laneLen = 64

// csrManager parameters, we use 3 csr for Post-processing SIMD
def csrNum: Int = 3 + 1

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Why separate 3+1?

It would be nice to have a description what these 3+1 are 😄

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Plus 1 for status CSR!

@xiaoling-yi xiaoling-yi merged commit c69eee0 into main Jan 24, 2024
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3 participants