add perf counter (#12)

src/main/scala/simd/CsrManager.scala

@@ -47,6 +47,7 @@ class CsrManagerIO(
   val csr_config_in = new CsrReqRspIO(csrAddrWidth)
   val csr_config_out = Decoupled(Vec(csrNum, UInt(32.W)))
 
+  val SIMDBusy2Idle = Input(Bool())
 }
 
 /** This class represents the CsrManager module. It contains the csr registers
@@ -69,7 +70,8 @@ class SIMDCsrManager(
 
   // read and write csr cmd
   val read_csr = io.csr_config_in.req.fire && !io.csr_config_in.req.bits.write
-  val write_csr = io.csr_config_in.req.fire && io.csr_config_in.req.bits.write
+  val write_csr =
+    (io.csr_config_in.req.fire || io.SIMDBusy2Idle) && io.csr_config_in.req.bits.write
 
   // keep sending response to a read request until we receive the response ready signal
   val keep_sending_csr_rsp = RegNext(
@@ -120,7 +122,7 @@ class SIMDCsrManager(
   // we are ready for a new request if two conditions hold:
   // if we write to the config_valid register (the last one), the streamer must not be busy (io.csr_config_out.ready)
   // if there is a read request in progress, we only accept new write requests
-  io.csr_config_in.req.ready := (io.csr_config_out.ready || !(io.csr_config_in.req.bits.addr === startCsrAddr)) && (!keep_sending_csr_rsp || io.csr_config_in.req.bits.write)
+  io.csr_config_in.req.ready := !io.SIMDBusy2Idle && (io.csr_config_out.ready || !(io.csr_config_in.req.bits.addr === startCsrAddr)) && (!keep_sending_csr_rsp || io.csr_config_in.req.bits.write)
 
   // a write/read to the last csr means the config is valid
   config_valid := io.csr_config_in.req.fire && (io.csr_config_in.req.bits.addr === startCsrAddr) && io.csr_config_in.req.bits.data === 1.U

src/main/scala/simd/Parameter.scala

@@ -15,8 +15,11 @@ object SIMDConstant {
   // SIMD parallelism
   def laneLen = 64
 
-  // csrManager parameters, we use 3 CSR for Post-processing SIMD configuration, 1 for the vector length, + 1 for status CSR
-  def csrNum: Int = 4 + 1
+  // csrManager parameters, we use 3 CSR for Post-processing SIMD configuration,
+  // CSR 4 for the vector length,
+  // CSR 5 for performance counter
+  // CSR 6 for status CSR (index is 5)
+  def csrNum: Int = 6
   def csrAddrWidth: Int = log2Up(csrNum)
 
 }

src/main/scala/simd/SIMD.scala

@@ -24,6 +24,8 @@ class SIMDIO extends Bundle {
   val ctrl = Flipped(Decoupled(new PECtrl()))
   // decoupled data ports
   val data = new SIMDDataIO()
+  val busy_o = Output(Bool())
+  val performance_counter = Output(UInt(32.W))
 }
 
 // post-processing SIMD module
@@ -86,6 +88,16 @@ class SIMD(laneLen: Int = SIMDConstant.laneLen)
     }
   }
 
+  io.busy_o := cstate === sBUSY
+
+  val performance_counter = RegInit(0.U(32.W))
+  when(cstate === sBUSY) {
+    performance_counter := performance_counter + 1.U
+  }.elsewhen(config_valid) {
+    performance_counter := 0.U
+  }
+  io.performance_counter := performance_counter
+
   config_valid := io.ctrl.fire
   // when config valid, store the configuration for later computation
   when(config_valid) {

src/main/scala/simd/SIMDTop.scala

@@ -19,7 +19,30 @@ class SIMDTop() extends Module with RequireAsyncReset {
   val simd = Module(new SIMD())
 
   // io.csr and SIMDCsrManager input connection
-  SIMDCsrManager.io.csr_config_in <> io.csr
+  // rsp port connected directly to the outside
+  SIMDCsrManager.io.csr_config_in.rsp <> io.csr.rsp
+
+  val csr_config_in_req_valid = WireInit(false.B)
+  val csr_config_in_req_bits = Wire(new CsrReq(SIMDConstant.csrAddrWidth))
+  val csr_config_in_req_ready = WireInit(false.B)
+
+  val simdBusy2Idle = WireInit(false.B)
+
+  simdBusy2Idle := !simd.io.busy_o && RegNext(simd.io.busy_o)
+  csr_config_in_req_valid := io.csr.req.valid
+  when(simdBusy2Idle) {
+    csr_config_in_req_bits.addr := SIMDConstant.csrNum.U - 2.U
+    csr_config_in_req_bits.data := simd.io.performance_counter
+    csr_config_in_req_bits.write := true.B
+  }.otherwise {
+    csr_config_in_req_bits := io.csr.req.bits
+  }
+
+  SIMDCsrManager.io.csr_config_in.req.valid := csr_config_in_req_valid
+  SIMDCsrManager.io.csr_config_in.req.bits := csr_config_in_req_bits
+  io.csr.req.ready := SIMDCsrManager.io.csr_config_in.req.ready
+
+  SIMDCsrManager.io.SIMDBusy2Idle := simdBusy2Idle
 
   // SIMDCsrManager output and simd control port connection
   // control signals

src/test/scala/simd/SIMDTopTest.scala

@@ -95,7 +95,7 @@ trait HasSIMDTopTestUtils extends HasSIMDTestUtils {
 
     // for start address
     var csr_3 = "x" + String.format("%02X", 4)
-    var csr_4 = "x" + String.format("%02X", 1)
+    var csr_5 = "x" + String.format("%02X", 1)
 
     // set configuration
     write_csr(dut, 0, csr_0)
@@ -104,7 +104,7 @@ trait HasSIMDTopTestUtils extends HasSIMDTestUtils {
     write_csr(dut, 3, csr_3)
 
     // start signal
-    write_csr(dut, 4, csr_4)
+    write_csr(dut, 5, csr_5)
 
     // read csr and check
     assert(csr_0.U(32.W).litValue == read_csr(dut, 0, "x00").litValue)