Add the mem wrappers and bender flags for the backend flow #56
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rgantonio
approved these changes
Oct 7, 2024
hw/spm_interface/src/spm_1p_adv.sv
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| // tc_sram_impl #( | ||
| // .NumWords (NumWords), | ||
| // .DataWidth(SPMDataWidth), | ||
| // .ByteWidth(ByteWidth), | ||
| // .NumPorts (1), | ||
| // .SimInit (SimInit), | ||
| // .PrintSimCfg (PrintSimCfg), | ||
| // .Latency (1), | ||
| // .impl_in_t (sram_cfg_t) | ||
| // ) i_mem ( | ||
| // .clk_i(clk_i), | ||
| // .rst_ni(rst_ni), | ||
| // .impl_i (sram_cfg_i), | ||
| // .impl_o ( ), | ||
| // .req_i(req_q), | ||
| // .we_i(we_q), | ||
| // .addr_i(addr_q), | ||
| // .wdata_i(wdata_q), | ||
| // .be_i(be_q), | ||
| // .rdata_o(rdata_sram) | ||
| // ); | ||
|
|
hw/spm_interface/src/spm_1p_adv.sv
Outdated
| @@ -253,4 +272,4 @@ module spm_1p_adv #( | |||
| assign rerror_q = rerror_d & {2{rvalid_d}}; | |||
| end | |||
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|||
| endmodule | |||
| endmodule | |||
| .rdata_o(rdata_o) | ||
| ); | ||
|
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||
| endmodule |
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| // for (genvar i = 0; i < ICACHE_SET_ASSOC; i++) begin : gen_sram | ||
| // // Tag RAM | ||
| // tc_sram_impl #( | ||
| // .impl_in_t ( sram_cfg_t ), | ||
| // // tag + valid bit | ||
| // .DataWidth ( ICACHE_TAG_WIDTH+1 ), | ||
| // .NumWords ( ICACHE_NUM_WORDS ), | ||
| // .NumPorts ( 1 ) | ||
| // ) tag_sram ( | ||
| // .clk_i ( clk_i ), | ||
| // .rst_ni ( rst_ni ), | ||
| // .impl_i ( sram_cfg_tag_i ), | ||
| // .impl_o ( ), | ||
| // .req_i ( vld_req[i] ), | ||
| // .we_i ( vld_we ), | ||
| // .addr_i ( vld_addr ), | ||
| // // we can always use the saved tag here since it takes a | ||
| // // couple of cycle until we write to the cache upon a miss | ||
| // .wdata_i ( {vld_wdata[i], cl_tag_q} ), | ||
| // .be_i ( '1 ), | ||
| // .rdata_o ( cl_tag_valid_rdata[i] ) | ||
| // ); | ||
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| // assign cl_tag_rdata[i] = cl_tag_valid_rdata[i][ICACHE_TAG_WIDTH-1:0]; | ||
| // assign vld_rdata[i] = cl_tag_valid_rdata[i][ICACHE_TAG_WIDTH]; | ||
|
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| // // Data RAM | ||
| // tc_sram_impl #( | ||
| // .impl_in_t ( sram_cfg_t ), | ||
| // .DataWidth ( ICACHE_LINE_WIDTH ), | ||
| // .NumWords ( ICACHE_NUM_WORDS ), | ||
| // .NumPorts ( 1 ) | ||
| // ) data_sram ( | ||
| // .clk_i ( clk_i ), | ||
| // .rst_ni ( rst_ni ), | ||
| // .impl_i ( sram_cfg_data_i ), | ||
| // .impl_o ( ), | ||
| // .req_i ( cl_req[i] ), | ||
| // .we_i ( cl_we ), | ||
| // .addr_i ( cl_index ), | ||
| // .wdata_i ( mem_rtrn_i.data ), | ||
| // .be_i ( '1 ), | ||
| // .rdata_o ( cl_rdata[i] ) | ||
| // ); | ||
|
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| // assign cl_ruser[i] = '0; | ||
| // end |
| @@ -564,4 +611,4 @@ end else begin : gen_piton_offset | |||
| `endif | |||
| //pragma translate_on | |||
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|||
| endmodule // cva6_icache | |||
| endmodule // cva6_icache | |||
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| // tc_sram_impl #( | ||
| // .impl_in_t ( sram_cfg_t ), | ||
| // .DataWidth ( 4*DCACHE_DIRTY_WIDTH ), | ||
| // .NumWords ( DCACHE_NUM_WORDS ), | ||
| // .NumPorts ( 1 ) | ||
| // ) valid_dirty_sram ( | ||
| // .clk_i ( clk_i ), | ||
| // .rst_ni ( rst_ni ), | ||
| // .impl_i ( sram_cfg_valid_dirty_i ), | ||
| // .impl_o ( ), | ||
| // .req_i ( |req_ram ), | ||
| // .we_i ( we_ram ), | ||
| // .addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ), | ||
| // .wdata_i ( dirty_wdata ), | ||
| // .be_i ( be_ram.vldrty ), | ||
| // .rdata_o ( dirty_rdata ) | ||
| // ); |
| @@ -297,4 +356,4 @@ import std_cache_pkg::*; | |||
| assert (DCACHE_LINE_WIDTH/AXI_DATA_WIDTH inside {2, 4, 8, 16}) else $fatal(1, "Cache line size needs to be a power of two multiple of AXI_DATA_WIDTH"); | |||
| end | |||
| //pragma translate_on | |||
| endmodule | |||
| endmodule | |||
| ); | ||
| end | ||
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| endmodule |
| ); | ||
| end | ||
|
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| endmodule |
| .rdata_o ( rdata_o ) | ||
| ); | ||
|
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||
| endmodule |
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IveanEx
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Nov 2, 2024
* Add the mem wrappers * Update the spm_1p_adv * clean newline and comments * remove the local snitch_read_only_cache_tb * Update some ports * update the snitch_ro_cache
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IveanEx
added a commit
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this pull request
Nov 2, 2024
* Add the mem wrappers and bender flags for the backend flow (#56) * Add the mem wrappers * Update the spm_1p_adv * clean newline and comments * remove the local snitch_read_only_cache_tb * Update some ports * update the snitch_ro_cache * Update the bender target (#59) * Fix I/O Error in occamy_chip.sv (#58) * Fix IO Error * Bug Fix * Bug Fix * Update Implementation Strategy * Update Implementation Strategy * Update the port definition of occamy_chip (#60) --------- Co-authored-by: Fanchen Kong <[email protected]>
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This PR adds the support for the memory wrappers at the host level.
Besides it also fix some problems on the occamy_chip
The bender flag is also updated to include the hemaia_chip_top with pads