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ppcd.cpp
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ppcd.cpp
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// Very accurate PowerPC Architecture disassembler (both 32 and 64-bit instructions are supported)
// Branch Target in output parameters is NOT relative. Its already precalculated
// from effective address of current instruction.
// Note, that old mnemonics and operands will be overwritten, after next disasm
// call. So dont forget to copy them away, if supposed to use them lately.
// Instruction class can be combined from many flags. There can exist, for example,
// "FPU" + "LDST" instruction, except "ILLEGAL", which cannot be combined.
// RLWINM-like instructions mask is placed in output "target" parameter.
#include <stdio.h>
#include <string.h>
//efine POWERPC_32 // Use generic 32-bit model
//efine POWERPC_64 // Use generic 64-bit model
#define GEKKO // Use Gekko (32-bit ISA)
//efine BROADWAY // Use Broadway (32-bit ISA)
#include "Commondefs.h"
#include "ppcd.h"
#define PRINT_ILLS // Print illegal instructions as ".int 0xYYYYYYYY"
#define SIMPLIFIED // Allow simplified mnemonics
//efine UPPERCASE // Use upper case strings in output
#define COMMA ", "
#define LPAREN " ("
#define RPAREN ")"
#define HEX1 "0x" // prefix
#define HEX2 "" // suffix
static int bigendian = -1; // Autodetect.
// ---------------------------------------------------------------------------
// Implementation. Look away, code is messed :)
// Dont miss 'l' and '1'.
static PPCD_CB *o;
#define Instr (o->instr)
#define DIS_PC (o->pc)
// Simple decoder
#define DIS_RD ((Instr >> 21) & 0x1f)
#define DIS_RS DIS_RD
#define DIS_RA ((Instr >> 16) & 0x1f)
#define DIS_RB ((Instr >> 11) & 0x1f)
#define DIS_RC ((Instr >> 6) & 0x1f)
#define DIS_RE ((Instr >> 1) & 0x1f)
#define DIS_MB DIS_RC
#define DIS_ME DIS_RE
#define DIS_OE (Instr & 0x400)
#define DIS_SIMM ((s16)Instr)
#define DIS_UIMM (Instr & 0xffff)
#define DIS_CRM ((Instr >> 12) & 0xff)
#define AA (Instr & 2)
#define LK (Instr & 1)
#define AALK (Instr & 3)
#define Rc LK
// GPRs. sp, sd1 and sd2 are named corresponding to PPC EABI.
static char *regname[] = {
#ifdef UPPERCASE
"R0" , "R1" , "R2", "R3" , "R4" , "R5" , "R6" , "R7" ,
"R8" , "R9" , "R10", "R11", "R12", "R13", "R14", "R15",
"R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
"R24", "R25", "R26", "R27", "R28", "R29", "R30", "R31"
#else
"r0" , "r1" , "r2", "r3" , "r4" , "r5" , "r6" , "r7" ,
"r8" , "r9" , "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
#endif
};
#define REGD (regname[DIS_RD])
#define REGS (regname[DIS_RS])
#define REGA (regname[DIS_RA])
#define REGB (regname[DIS_RB])
// Illegal instruction.
static void ill(void)
{
#ifdef PRINT_ILLS
#ifdef UPPERCASE
strcpy(o->mnemonic, ".INT");
#else
strcpy(o->mnemonic, ".int");
#endif
sprintf(o->operands, HEX1 "%08X" HEX2, Instr);
#else
o->mnemonic[0] = o->operands[0] = '\0';
#endif
o->iclass = PPC_DISA_ILLEGAL;
}
// Smart SIMM formatting (if hex=1, then force HEX; if s=1, use sign)
static char * simm(int val, int hex, int s)
{
static char out[16];
if (((val >= -256) && (val <= 256)) && !hex) sprintf(out, "%i", val);
else
{
u16 hexval = (u16)val;
if ((hexval & 0x8000) && s) sprintf(out, "-" HEX1 "%04X" HEX2, ((~hexval) & 0xffff) + 1);
else sprintf(out, HEX1 "%04X" HEX2, hexval);
}
return out;
}
// Simple instruction form + reserved bitmask.
static void put(char * mnem, u32 mask, u32 chkval = 0, int iclass = PPC_DISA_OTHER)
{
if ((Instr & mask) != chkval) { ill(); return; }
o->iclass |= iclass;
strncpy(o->mnemonic, mnem, sizeof(o->mnemonic));
}
// Simplified mnemonic trap conditions
static char * t_cond[32] = {
NULL, "lgt", "llt", NULL, "eq", "lge", "lle", NULL,
"gt", NULL, NULL, NULL, "ge", NULL, NULL, NULL,
"lt", NULL, NULL, NULL, "le", NULL, NULL, NULL,
"ne", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};
// Trap instructions.
static void trap(int L, int imm)
{
static char t_mode[2] = { 'w', 'd' };
int rd = DIS_RD; // TO
int s = (rd & 0x18) ? 1 : 0;
#ifdef SIMPLIFIED
if (t_cond[rd] != NULL)
{
sprintf(o->mnemonic, "t%c%s%c", t_mode[L & 1], t_cond[rd], imm ? 'i' : 0);
if (imm) sprintf(o->operands, "%s" COMMA "%s", REGA, simm(DIS_SIMM, 0, s));
else sprintf(o->operands, "%s" COMMA "%s", REGA, REGB);
o->iclass |= PPC_DISA_SIMPLIFIED;
}
else
#endif
{
sprintf(o->mnemonic, "t%c%c", t_mode[L & 1], imm ? 'i' : 0);
if (imm) sprintf(o->operands, "%i" COMMA "%s" COMMA "%s", rd, REGA, simm(DIS_SIMM, 0, s));
else sprintf(o->operands, "%i" COMMA "%s" COMMA "%s", rd, REGA, REGB);
}
if (L) o->iclass |= PPC_DISA_64;
o->r[1] = DIS_RA; if (!imm) o->r[2] = DIS_RB;
if (imm)
{
o->immed = Instr & 0xFFFF;
if (o->immed & 0x8000) o->immed |= 0xFFFF0000;
}
}
// DAB mask
#define DAB_D 4
#define DAB_A 2
#define DAB_B 1
// ASB mask
#define ASB_A 4
#define ASB_S 2
#define ASB_B 1
// cr%i
#ifdef UPPERCASE
static char crname[] = "CR";
#else
static char crname[] = "cr";
#endif
// f%i
#ifdef UPPERCASE
static char fregname[] = "F";
#else
static char fregname[] = "f";
#endif
// Integer instructions
// form: 'D' rD, rA, (s)IMM
// 'S' rA, rS, (s)IMM
// 'X' rD, rA, rB
// 'Z' rA, rS, rB
// 'F' frD, rA, rB
// dab LSB bits : [D][A][B] (D should always present)
// 'hex' for logic opcodes, 's' for alu opcodes, 'crfD' and 'L' for cmp opcodes
// 'imm': 1 to show immediate operand
static void integer(char *mnem, char form, int dab, int hex = 0, int s = 1, int crfD = 0, int L = 0, int imm = 1)
{
char * ptr = o->operands;
int rd = DIS_RD, ra = DIS_RA, rb = DIS_RB;
strncpy(o->mnemonic, mnem, sizeof(o->mnemonic));
if (crfD) ptr += sprintf(ptr, "%s%i" COMMA, crname, rd >> 2); // CMP only
if (L) ptr += sprintf(ptr, "%i" COMMA, rd & 1); // CMP only
if (form == 'D')
{
if (dab & DAB_D) ptr += sprintf(ptr, "%s", REGD);
if (dab & DAB_A)
{
if (dab & DAB_D) ptr += sprintf(ptr, "%s", COMMA);
ptr += sprintf(ptr, "%s", REGA);
}
if (imm) ptr += sprintf(ptr, COMMA "%s", simm(s ? DIS_SIMM : DIS_UIMM, hex, s));
}
else if (form == 'S')
{
if (dab & ASB_A) ptr += sprintf(ptr, "%s", REGA);
if (dab & ASB_S)
{
if (dab & ASB_A) ptr += sprintf(ptr, "%s", COMMA);
ptr += sprintf(ptr, "%s", REGS);
}
if (imm) ptr += sprintf(ptr, COMMA "%s", simm(s ? DIS_SIMM : DIS_UIMM, hex, s));
}
else if (form == 'X') // DAB
{
if (dab & DAB_D) ptr += sprintf(ptr, "%s", REGD);
if (dab & DAB_A)
{
if (dab & DAB_D) ptr += sprintf(ptr, "%s", COMMA);
ptr += sprintf(ptr, "%s", REGA);
}
if (dab & DAB_B)
{
if (dab & (DAB_D | DAB_A)) ptr += sprintf(ptr, "%s", COMMA);
ptr += sprintf(ptr, "%s", REGB);
}
}
else if (form == 'F') // FPU DAB
{
if (dab & DAB_D) ptr += sprintf(ptr, "%s%i", fregname, rd);
if (dab & DAB_A)
{
if (dab & DAB_D) ptr += sprintf(ptr, "%s", COMMA);
ptr += sprintf(ptr, "%s", REGA);
}
if (dab & DAB_B)
{
if (dab & (DAB_D | DAB_A)) ptr += sprintf(ptr, "%s", COMMA);
ptr += sprintf(ptr, "%s", REGB);
}
}
else if (form == 'Z') // ASB
{
if (dab & ASB_A) ptr += sprintf(ptr, "%s", REGA);
if (dab & ASB_S)
{
if (dab & ASB_A) ptr += sprintf(ptr, "%s", COMMA);
ptr += sprintf(ptr, "%s", REGS);
}
if (dab & ASB_B)
{
if (dab & (ASB_A | ASB_S)) ptr += sprintf(ptr, "%s", COMMA);
ptr += sprintf(ptr, "%s", REGB);
}
}
else { ill(); return; }
if (form == 'D' || form == 'X' || form == 'F') { o->r[0] = rd; o->r[1] = ra; }
if (form == 'S' || form == 'Z') { o->r[0] = ra; o->r[1] = rd; }
if (form == 'X' || form == 'Z' || form == 'F') o->r[2] = rb;
if ((form == 'D' || form == 'S') && imm)
{
o->immed = Instr & 0xFFFF;
if (o->immed & 0x8000 && s) o->immed |= 0xFFFF0000;
}
o->iclass |= PPC_DISA_INTEGER;
}
// Compare instructions (wraps to integer call)
static void cmp(char *l, char *i)
{
char mnem[sizeof(o->mnemonic)];
int rd = DIS_RD;
if (rd & 2) { ill(); return; } // Reserved bit set
if (rd & 1)
{
#ifndef POWERPC_64
{ ill(); return; }
#endif
o->iclass |= PPC_DISA_64;
}
#ifdef SIMPLIFIED
sprintf(mnem, "cmp%s%c%s", l, (rd & 1) ? 'd' : 'w', i);
integer(mnem, (*i == 'i') ? 'D' : 'X', DAB_A | DAB_B, 0, (*l == 'l') ? 0 : 1, (rd >> 2) ? 1 : 0, 0);
o->iclass |= PPC_DISA_SIMPLIFIED;
#else
sprintf(mnem, "cmp%s%s", l, i);
integer(mnem, (*i == 'i') ? 'D' : 'X', DAB_A | DAB_B, 0, 1, 1, 1);
#endif
}
// Add immediate (wraps to integer call)
static void addi(char *suffix)
{
char mnem[sizeof(o->mnemonic)];
#ifdef SIMPLIFIED
if ((suffix[0] == '\0') && (DIS_RA == 0)) // Load immediate
{
integer("li", 'D', DAB_D, 0, 1);
o->iclass |= PPC_DISA_SIMPLIFIED;
return;
}
if ((suffix[0] == 's') && (DIS_RA == 0)) // Load address HI
{
integer("lis", 'D', DAB_D, 1, 0);
o->iclass |= PPC_DISA_SIMPLIFIED;
return;
}
if (DIS_UIMM & 0x8000)
{
sprintf(mnem, "subi%s", suffix);
// Fix immediate field.
u16 value = (u16)(~(DIS_UIMM)+1);
Instr = (Instr & ~0xFFFF) | value;
integer(mnem, 'D', DAB_D | DAB_A, 0, 0);
o->iclass |= PPC_DISA_SIMPLIFIED;
}
else
{
sprintf(mnem, "addi%s", suffix);
integer(mnem, 'D', DAB_D | DAB_A, 0, 0);
}
#else
sprintf(mnem, "addi%s", suffix);
integer(mnem, 'D', DAB_D | DAB_A);
#endif
}
// Branch suffix: AA || LK.
static char *b_opt[4] = { "", "l", "a", "la" };
// Branch condition code: 4 * BO[1] + (BI & 3)
static char * b_cond[8] = {
"ge", "le", "ne", "ns", "lt", "gt", "eq", "so"
};
// Branch on CTR code: BO[0..3]
static char * b_ctr[16] = {
"dnzf", "dzf", NULL, NULL, "dnzt", "dzt", NULL, NULL,
"dnz", "dz", NULL, NULL, NULL, NULL, NULL, NULL
};
// Place target address in operands. Helper for bcx/bx calls.
static char *place_target(char *ptr, int comma)
{
char *old;
u32 *t = (u32 *)&o->target;
if (comma) ptr += sprintf(ptr, "%s", COMMA);
old = ptr;
#if defined POWERPC_32 \
|| defined GEKKO
ptr += sprintf(ptr, "loc_%08X" HEX2, (u32)o->target);
#endif
#ifdef POWERPC_64
ptr = old;
if (bigendian) ptr += sprintf(ptr, HEX1 "%08X_%08X" HEX2, t[0], t[1]);
else ptr += sprintf(ptr, HEX1 "%08X_%08X" HEX2, t[1], t[0]);
#endif
return ptr;
}
// Branch conditional.
// Disp:1 - branch with displacement..
// Disp:0 - branch by register (L:1 for LR, L:0 for CTR).
static void bcx(int Disp, int L)
{
u64 bd = 0;
int bo = DIS_RD, bi = DIS_RA;
char *r = Disp ? "" : (L ? "lr" : "ctr");
char *ptr = o->operands;
if (DIS_RB && !Disp) { ill(); return; }
o->operands[0] = '\0';
o->target = 0;
o->iclass |= PPC_DISA_BRANCH;
// Calculate displacement and target address
if (Disp)
{
bd = DIS_UIMM & ~3;
if (bd & 0x8000) bd |= 0xffffffffffff0000;
o->target = (AA ? 0 : DIS_PC) + bd;
}
else o->target = 0;
// Calculate branch prediction hint
char y = (bo & 1) ^ ((((s64)bd < 0) && Disp) ? 1 : 0);
y = y ? '+' : '-';
if (bo & 4) // No CTR decrement // BO[2]
{
if (bo & 16) // Branch always // BO[0]
{
#ifdef SIMPLIFIED
sprintf(o->mnemonic, "b%s%s", r, b_opt[Disp ? AALK : LK]);
if (Disp) ptr = place_target(ptr, 0);
o->iclass |= PPC_DISA_SIMPLIFIED;
return;
#endif // SIMPLIFIED
}
else // Branch conditional
{
if (bo & 2) { ill(); return; } // BO[3]
#ifdef SIMPLIFIED
char *cond = b_cond[((bo & 8) >> 1) | (bi & 3)];
if (cond != NULL) // BO[1]
{
sprintf(o->mnemonic, "b%s%s%s%c", cond, r, b_opt[Disp ? AALK : LK], y);
if (bi >= 4) ptr += sprintf(ptr, "%s%i", crname, bi >> 2);
if (Disp) ptr = place_target(ptr, bi >= 4);
o->iclass |= PPC_DISA_SIMPLIFIED;
return;
}
#endif // SIMPLIFIED
}
}
else // Decrement CTR
{
if (!L && !Disp) { ill(); return; }
if (bo & 8) { ill(); return; } // BO[1]
#ifdef SIMPLIFIED
if (b_ctr[bo >> 1])
{
sprintf(o->mnemonic, "b%s%s%s%c", b_ctr[bo >> 1], r, b_opt[Disp ? AALK : LK], y);
if (!(bo & 16)) ptr += sprintf(ptr, "%i", bi);
if (Disp) ptr = place_target(ptr, !(bo & 16));
o->iclass |= PPC_DISA_SIMPLIFIED;
return;
}
#endif // SIMPLIFIED
}
// Not simplified standard form
sprintf(o->mnemonic, "bc%s%s", r, b_opt[Disp ? AALK : LK]);
ptr += sprintf(ptr, "%i" COMMA "%i", bo, bi);
if (Disp) ptr = place_target(ptr, 1);
}
// Branch unconditional
static void bx(void)
{
// Calculate displacement and target address
u64 bd = Instr & 0x03fffffc;
if (bd & 0x02000000)
bd |= 0xfffffffffc000000;
o->target = (AA ? 0 : DIS_PC) + bd;
o->iclass |= PPC_DISA_BRANCH;
sprintf(o->mnemonic, "b%s", b_opt[AALK]);
place_target(o->operands, 0);
}
// Move CR field
static void mcrf(void)
{
if (Instr & 0x63f801) { ill(); return; }
strncpy(o->mnemonic, "mcrf", sizeof(o->mnemonic));
sprintf(o->operands, "%s%i" COMMA "%s%i", crname, DIS_RD >> 2, crname, DIS_RA >> 2);
}
// CR logic operations
static void crop(char *name, char *simp = "", int ddd = 0, int daa = 0)
{
if (Instr & 1) { ill(); return; }
int crfD = DIS_RD, crfA = DIS_RA, crfB = DIS_RB;
#ifdef SIMPLIFIED
if (crfA == crfB)
{
if ((crfD == crfA) && ddd)
{
sprintf(o->mnemonic, "cr%s", simp);
sprintf(o->operands, "%i", crfD);
o->r[0] = crfD;
o->iclass |= PPC_DISA_SIMPLIFIED;
return;
}
if (daa)
{
sprintf(o->mnemonic, "cr%s", simp);
sprintf(o->operands, "%i" COMMA "%i", crfD, crfA);
o->r[0] = crfD; o->r[1] = crfA;
o->iclass |= PPC_DISA_SIMPLIFIED;
return;
}
}
#endif
sprintf(o->mnemonic, "cr%s", name);
sprintf(o->operands, "%i" COMMA "%i" COMMA "%i", crfD, crfA, crfB);
o->r[0] = crfD; o->r[1] = crfA; o->r[2] = crfB;
}
#define MASK32(b, e) \
{ \
u32 _mask = ((u32)0xffffffff >> (b)) ^ (((e) >= 31) ? 0 : ((u32)0xffffffff) >> ((e) + 1)); \
o->mask = ((b) > (e)) ? (~_mask) : (_mask); \
}
#define MASK64(b, e) \
{ \
u64 _mask = ((u64)0xffffffffffffffff >> (b)) ^ (((e) >= 63) ? 0 : ((u64)0xffffffffffffffff) >> ((e) + 1)); \
o->mask = ((b) > (e)) ? (~_mask) : (_mask); \
}
// Rotate left word.
static void rlw(char *name, int rb, int ins = 0)
{
int mb = DIS_MB, me = DIS_ME;
char * ptr = o->operands;
sprintf(o->mnemonic, "rlw%s%c", name, Rc ? '.' : '\0');
ptr += sprintf(ptr, "%s" COMMA "%s" COMMA, REGA, REGS);
if (rb) ptr += sprintf(ptr, "%s" COMMA, REGB);
else ptr += sprintf(ptr, "%i" COMMA, DIS_RB); // sh
ptr += sprintf(ptr, "%i" COMMA "%i", mb, me);
// Put mask into 'mask'.
MASK32(mb, me);
#ifdef POWERPC_64
MASK64(mb + 32, me + 32);
#endif
o->r[0] = DIS_RA;
o->r[1] = DIS_RS;
if (rb) o->r[2] = DIS_RB;
o->iclass |= PPC_DISA_INTEGER;
}
// RLD mask
#define RLDM_LEFT 0 // MASK(b, 63)
#define RLDM_RIGHT 1 // MASK(0, e)
#define RLDM_INS 2 // MASK(b, ~n)
// Rotate left double-word.
static void rld(char *name, int rb, int mtype)
{
#ifdef POWERPC_64
int m = DIS_MB, n = DIS_RB;
if (Instr & 0x20) m += 32; // b or e
if (Instr & 0x02) n += 32; // sh
char * ptr = o->operands;
sprintf(o->mnemonic, "rld%s%c", name, Rc ? '.' : '\0');
ptr += sprintf(ptr, "%s" COMMA "%s" COMMA, REGA, REGS);
if (rb) ptr += sprintf(ptr, "%s" COMMA, REGB);
else ptr += sprintf(ptr, "%i" COMMA, n);
ptr += sprintf(ptr, "%i", m);
// Put mask into 'mask'.
switch (mtype)
{
case RLDM_LEFT: MASK64(m, 63); break;
case RLDM_RIGHT: MASK64(0, m); break;
case RLDM_INS: MASK64(m, ~n); break;
}
o->r[0] = DIS_RA;
o->r[1] = DIS_RS;
if (rb) o->r[2] = DIS_RB;
o->iclass |= PPC_DISA_64 | PPC_DISA_INTEGER;
#endif
}
// Load/Store.
static void ldst(char *name, int x/*indexed*/, int load = 1, int L = 0, int string = 0, int fload = 0)
{
if (x) integer(name, fload ? 'F' : 'X', DAB_D | DAB_A | DAB_B);
else
{
int rd = DIS_RD, ra = DIS_RA;
s16 imm = DIS_SIMM;
strcpy(o->mnemonic, name);
if (fload) sprintf(o->operands, "%s%i" COMMA "%s" LPAREN "%s" RPAREN, fregname, rd, simm(imm, 0, 1), regname[ra]);
else sprintf(o->operands, "%s" COMMA "%s" LPAREN "%s" RPAREN, regname[rd], simm(imm, 0, 1), regname[ra]);
o->r[0] = rd;
o->r[1] = ra;
o->immed = DIS_UIMM & 0x8000 ? DIS_UIMM | 0xFFFF0000 : DIS_UIMM;
}
o->iclass = PPC_DISA_LDST;
if (L) o->iclass |= PPC_DISA_64;
if (string) o->iclass |= PPC_DISA_STRING;
if (fload) o->iclass |= PPC_DISA_FPU;
}
// Cache.
static void cache(char *name, int flag = PPC_DISA_OTHER)
{
if (DIS_RD) { ill(); return; }
else
{
integer(name, 'X', DAB_A | DAB_B);
o->r[0] = o->r[1];
o->r[1] = o->r[2];
o->r[2] = 0;
o->iclass &= ~PPC_DISA_INTEGER;
o->iclass |= flag;
}
}
static void movesr(char *name, int from, int L, int xform)
{
int reg = DIS_RD, sreg = DIS_RA & 0xF, regb = DIS_RB;
strncpy(o->mnemonic, name, sizeof(o->mnemonic));
if (xform)
{
if (Instr & 0x001F0001) { ill(); return; }
sprintf(o->operands, "%s" COMMA "%s", regname[reg], regname[regb]);
o->r[0] = reg;
o->r[1] = regb;
}
else
{
if (Instr & 0x0010F801) { ill(); return; }
if (from)
{
sprintf(o->operands, "%s" COMMA "%i", regname[reg], sreg);
o->r[0] = reg;
o->r[1] = sreg;
}
else
{
sprintf(o->operands, "%i" COMMA "%s", sreg, regname[reg]);
o->r[0] = sreg;
o->r[1] = reg;
}
}
if (L) o->iclass |= PPC_DISA_OEA | PPC_DISA_OPTIONAL | PPC_DISA_BRIDGE | PPC_DISA_64;
else o->iclass |= PPC_DISA_OEA | PPC_DISA_BRIDGE;
}
static void mtcrf(void)
{
int rs = DIS_RS, crm = DIS_CRM;
#ifdef SIMPLIFIED
if (crm == 0xFF)
{
strncpy(o->mnemonic, "mtcr", sizeof(o->mnemonic));
sprintf(o->operands, "%s", regname[rs]);
}
else
#endif
{
strncpy(o->mnemonic, "mtcrf", sizeof(o->mnemonic));
sprintf(o->operands, HEX1 "%02X" HEX2 COMMA "%s", crm, regname[rs]);
}
o->r[0] = rs;
}
static void mcrxr(void)
{
if (Instr & 0x007FF800) { ill(); return; }
strcpy(o->mnemonic, "mcrxr");
sprintf(o->operands, "%s%i", crname, DIS_RD >> 2);
o->r[0] = DIS_RD >> 2;
}
static char *spr_name(int n)
{
static char def[8];
switch (n)
{
// General architecture special-purpose registers.
case 1: return "XER";
case 8: return "LR";
case 9: return "CTR";
case 18: return "DSISR";
case 19: return "DAR";
case 22: return "DEC";
case 25: return "SDR1";
case 26: return "SRR0";
case 27: return "SRR1";
case 272: return "SPRG0";
case 273: return "SPRG1";
case 274: return "SPRG2";
case 275: return "SPRG3";
#ifdef POWERPC_64
case 280: return "ASR";
#endif
case 284: return "TBL";
case 285: return "TBU";
case 287: return "PVR";
case 528: return "IBAT0U";
case 529: return "IBAT0L";
case 530: return "IBAT1U";
case 531: return "IBAT1L";
case 532: return "IBAT2U";
case 533: return "IBAT2L";
case 534: return "IBAT3U";
case 535: return "IBAT3L";
case 536: return "DBAT0U";
case 537: return "DBAT0L";
case 538: return "DBAT1U";
case 539: return "DBAT1L";
case 540: return "DBAT2U";
case 541: return "DBAT2L";
case 542: return "DBAT3U";
case 543: return "DBAT3L";
// Optional registers.
#if !defined(GEKKO) && !defined(BROADWAY)
case 282: return "EAR";
case 1013: return "DABR";
case 1022: return "FPECR";
case 1023: return "PIR";
#endif
// Gekko-specific SPRs
#ifdef GEKKO
case 282: return "EAR";
case 912: return "GQR0";
case 913: return "GQR1";
case 914: return "GQR2";
case 915: return "GQR3";
case 916: return "GQR4";
case 917: return "GQR5";
case 918: return "GQR6";
case 919: return "GQR7";
case 920: return "HID2";
case 921: return "WPAR";
case 922: return "DMAU";
case 923: return "DMAL";
case 936: return "UMMCR0";
case 940: return "UMMCR1";
case 937: return "UPMC1";
case 938: return "UPMC2";
case 939: return "USIA";
case 941: return "UPMC3";
case 942: return "UPMC4";
case 943: return "USDA";
case 952: return "MMCR0";
case 953: return "PMC1";
case 954: return "PMC2";
case 955: return "SIA";
case 956: return "MMCR1";
case 957: return "PMC3";
case 958: return "PMC4";
case 959: return "SDA";
case 1008: return "HID0";
case 1009: return "HID1";
case 1010: return "IABR";
case 1013: return "DABR";
case 1017: return "L2CR";
case 1019: return "ICTC";
case 1020: return "THRM1";
case 1021: return "THRM2";
case 1022: return "THRM3";
#endif
}
sprintf(def, "%u", n);
return def;
}
static char *tbr_name(int n)
{
static char def[8];
switch (n)
{
// General architecture time-base registers.
case 268: return "TBL";
case 269: return "TBU";
}
sprintf(def, "%u", n);
return def;
}
static void movespr(int from)
{
int spr = (DIS_RB << 5) | DIS_RA, f = 1;
char *fix;
if (!((spr == 1) || (spr == 8) || (spr == 9))) o->iclass |= PPC_DISA_OEA;
// Handle simplified mnemonic
if (spr == 1) { fix = "xer"; o->iclass |= PPC_DISA_SIMPLIFIED; }
else if (spr == 8) { fix = "lr"; o->iclass |= PPC_DISA_SIMPLIFIED; }
else if (spr == 9) { fix = "ctr"; o->iclass |= PPC_DISA_SIMPLIFIED; }
else { fix = "spr"; f = 0; }
// Mnemonics and operands.
sprintf(o->mnemonic, "m%c%s", from ? 'f' : 't', fix);
if (f)
{
sprintf(o->operands, "%s", regname[DIS_RD]);
o->r[0] = DIS_RD;
}
else
{
if (from)
{
sprintf(o->operands, "%s" COMMA "%s", regname[DIS_RD], spr_name(spr));
o->r[0] = DIS_RD;
o->r[1] = spr;
}
else
{
sprintf(o->operands, "%s" COMMA "%s", spr_name(spr), regname[DIS_RD]);
o->r[0] = spr;
o->r[1] = DIS_RD;
}
}
}
static void movetbr(void)
{
int tbr = (DIS_RB << 5) | DIS_RA, f = 1;
char *fix;
// Handle simplified mnemonic
if (tbr == 268) { fix = "tbl"; o->iclass |= PPC_DISA_SIMPLIFIED; }
else if (tbr == 269) { fix = "tbu"; o->iclass |= PPC_DISA_SIMPLIFIED; }
else { fix = "tb"; f = 0; }
// Mnemonics and operands.
sprintf(o->mnemonic, "mf%s", fix);
if (f)
{
sprintf(o->operands, "%s", regname[DIS_RD]);
o->r[0] = DIS_RD;
}
else
{
sprintf(o->operands, "%s" COMMA "%s", regname[DIS_RD], tbr_name(tbr));
o->r[0] = DIS_RD;
o->r[1] = tbr;
}
}
static void srawi(void)
{
int rs = DIS_RS, ra = DIS_RA, sh = DIS_RB;
sprintf(o->mnemonic, "srawi%c", Rc ? '.' : 0);
sprintf(o->operands, "%s" COMMA "%s" COMMA "%i", regname[ra], regname[rs], sh);
o->r[0] = ra;
o->r[1] = rs;
o->r[2] = sh;
o->iclass = PPC_DISA_INTEGER;
}
static void sradi(void)
{
int rs = DIS_RS, ra = DIS_RA, sh = (((Instr >> 1) & 1) << 5) | DIS_RB;
sprintf(o->mnemonic, "sradi%c", Rc ? '.' : 0);
sprintf(o->operands, "%s" COMMA "%s" COMMA "%i", regname[ra], regname[rs], sh);
o->r[0] = ra;
o->r[1] = rs;
o->r[2] = sh;
o->iclass = PPC_DISA_INTEGER | PPC_DISA_64;
}
static void lsswi(char *name)
{
int rd = DIS_RD, ra = DIS_RA, nb = DIS_RB;
strcpy(o->mnemonic, name);
sprintf(o->operands, "%s" COMMA "%s" COMMA "%i", regname[rd], regname[ra], nb);
o->r[0] = rd;
o->r[1] = ra;
o->r[2] = nb;
o->iclass = PPC_DISA_LDST | PPC_DISA_STRING;
}
#define FPU_DAB 1
#define FPU_DB 2
#define FPU_DAC 3
#define FPU_DACB 4
#define FPU_D 5
static void fpu(char *name, u32 mask, int type, int flag = PPC_DISA_OTHER)
{
int d = DIS_RD, a = DIS_RA, c = DIS_RC, b = DIS_RB;
if (Instr & mask) { ill(); return; }
strcpy(o->mnemonic, name);
switch (type)
{
case FPU_DAB:
sprintf(o->operands, "%s%i" COMMA "%s%i" COMMA "%s%i", fregname, d, fregname, a, fregname, b);
o->r[0] = d; o->r[1] = a; o->r[2] = b;
break;
case FPU_DB:
sprintf(o->operands, "%s%i" COMMA "%s%i", fregname, d, fregname, b);
o->r[0] = d; o->r[1] = b;
break;
case FPU_DAC:
sprintf(o->operands, "%s%i" COMMA "%s%i" COMMA "%s%i", fregname, d, fregname, a, fregname, c);
o->r[0] = d; o->r[1] = a; o->r[2] = c;
break;
case FPU_DACB:
sprintf(o->operands, "%s%i" COMMA "%s%i" COMMA "%s%i" COMMA "%s%i", fregname, d, fregname, a, fregname, c, fregname, b);
o->r[0] = d; o->r[1] = a; o->r[2] = c; o->r[3] = b;
break;
case FPU_D:
sprintf(o->operands, "%s%i", fregname, d);
o->r[0] = d;
break;
}
o->iclass = PPC_DISA_FPU | flag;
}
static void fcmp(char *name)
{
int crfd = DIS_RD >> 2, ra = DIS_RA, rb = DIS_RB;
if (Instr & 0x00600001) { ill(); return; }
strcpy(o->mnemonic, name);
sprintf(o->operands, "%i" COMMA "%s%i" COMMA "%s%i", crfd, fregname, ra, fregname, rb);
o->r[0] = crfd; o->r[1] = ra; o->r[2] = rb;
o->iclass = PPC_DISA_FPU;
}
static void mtfsf(void)
{
int fm = (Instr >> 17) & 0xFF, rb = DIS_RB;
if (Instr & 0x02010000) { ill(); return; }
sprintf(o->mnemonic, "mtfsf%c", Rc ? '.' : 0);
sprintf(o->operands, HEX1 "%02X" HEX2 COMMA "%s%i", fm, fregname, rb);
o->r[0] = fm; o->r[1] = rb;
o->iclass = PPC_DISA_FPU;
}
static void mtfsb(char *name)
{
int crbd = DIS_RD;
if (Instr & 0x001FF800) { ill(); return; }
strcpy(o->mnemonic, name);
sprintf(o->operands, "%i", crbd);
o->r[0] = crbd;
o->iclass = PPC_DISA_FPU;
}
static void mcrfs(void)
{
int crfD = DIS_RD >> 2, crfS = DIS_RA >> 2;
if (Instr & 0x0063F801) { ill(); return; }
strcpy(o->mnemonic, "mcrfs");
sprintf(o->operands, "%s%i" COMMA "%s%i", crname, crfD, crname, crfS);
o->r[0] = crfD; o->r[1] = crfS;
o->iclass = PPC_DISA_FPU;
}
static void mtfsfi(void)
{
int crfD = DIS_RD >> 2, imm = DIS_RB >> 1;
if (Instr & 0x007F0800) { ill(); return; }
sprintf(o->mnemonic, "mtfsfi%c", Rc ? '.' : 0);
sprintf(o->operands, "%s%i" COMMA "%i", crname, crfD, imm);
o->r[0] = crfD; o->r[1] = imm;
o->iclass = PPC_DISA_FPU;
}
/*
***********************************************************************************
* Architecture-specific extensions:
* Processor model: GEKKO
***********************************************************************************
*/
#ifdef GEKKO
static void ps_cmpx(int n)
{
static char *fix[] = { "u0", "o0", "u1", "o1" };
if (Instr & 0x00600001) { ill(); return; }
sprintf(o->mnemonic, "ps_cmp%s", fix[n]);
o->r[0] = DIS_RD >> 2; o->r[1] = DIS_RA; o->r[2] = DIS_RB;
sprintf(o->operands, "%s%d" COMMA "%s%d" COMMA "%s%d", crname, o->r[0], fregname, o->r[1], fregname, o->r[2]);
o->iclass = PPC_DISA_FPU | PPC_DISA_SPECIFIC;
}
static char *ps_ldst_offs(unsigned long val)
{