GitHub - Farheen-github/ECE552: A 16-bit 5-stage in-order pipelined processor in Verilog with Direct Mapped and Set Associative write back Cache.

Farheen-github / ECE552 Public

Notifications You must be signed in to change notification settings
Fork 0
Star 0

A 16-bit 5-stage in-order pipelined processor in Verilog with Direct Mapped and Set Associative write back Cache.

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
CLA_block.v		CLA_block.v
Dcache_0_data_0		Dcache_0_data_0
Dcache_0_data_1		Dcache_0_data_1
Dcache_0_data_2		Dcache_0_data_2
Dcache_0_data_3		Dcache_0_data_3
Dcache_0_dirty		Dcache_0_dirty
Dcache_0_tags		Dcache_0_tags
Dcache_0_valid		Dcache_0_valid
Dcache_1_data_0		Dcache_1_data_0
Dcache_1_data_1		Dcache_1_data_1
Dcache_1_data_2		Dcache_1_data_2
Dcache_1_data_3		Dcache_1_data_3
Dcache_1_dirty		Dcache_1_dirty
Dcache_1_tags		Dcache_1_tags
Dcache_1_valid		Dcache_1_valid
Icache_0_data_0		Icache_0_data_0
Icache_0_data_1		Icache_0_data_1
Icache_0_data_2		Icache_0_data_2
Icache_0_data_3		Icache_0_data_3
Icache_0_dirty		Icache_0_dirty
Icache_0_tags		Icache_0_tags
Icache_0_valid		Icache_0_valid
Icache_1_data_0		Icache_1_data_0
Icache_1_data_1		Icache_1_data_1
Icache_1_data_2		Icache_1_data_2
Icache_1_data_3		Icache_1_data_3
Icache_1_dirty		Icache_1_dirty
Icache_1_tags		Icache_1_tags
Icache_1_valid		Icache_1_valid
PC_calc1.v		PC_calc1.v
PC_calc2.v		PC_calc2.v
PC_calc3.v		PC_calc3.v
Reg.v		Reg.v
alu.v		alu.v
alu_hier.v		alu_hier.v
archsim.out		archsim.out
archsim.ptrace		archsim.ptrace
archsim.trace		archsim.trace
arithmetic.v		arithmetic.v
cache.v		cache.v
cla_16b.v		cla_16b.v
cla_4b.v		cla_4b.v
clkrst.v		clkrst.v
decode.v		decode.v
decoder_w_en.v		decoder_w_en.v
demo2_wcache.mpf		demo2_wcache.mpf
dff.v		dff.v
dumpfile_0		dumpfile_0
dumpfile_1		dumpfile_1
dumpfile_2		dumpfile_2
dumpfile_3		dumpfile_3
execute.v		execute.v
fetch.v		fetch.v
final_memory.syn.v		final_memory.syn.v
final_memory.v		final_memory.v
forward_detection.v		forward_detection.v
four_bank_mem.v		four_bank_mem.v
fullAdder_1b.v		fullAdder_1b.v
hazard_detector.v		hazard_detector.v
largest		largest
latch_exmem.v		latch_exmem.v
latch_idex.v		latch_idex.v
latch_ifid.v		latch_ifid.v
latch_memwb.v		latch_memwb.v
leftshift_block.v		leftshift_block.v
loadfile.lst		loadfile.lst
loadfile_0.img		loadfile_0.img
loadfile_1.img		loadfile_1.img
loadfile_2.img		loadfile_2.img
loadfile_3.img		loadfile_3.img
loadfile_all.img		loadfile_all.img
loadfile_all.img.dmem		loadfile_all.img.dmem
loadfile_all.img.reg		loadfile_all.img.reg
maincontrol.v		maincontrol.v
mem_controller.v		mem_controller.v
mem_system.v		mem_system.v
mem_system_hier.v		mem_system_hier.v
mem_system_perfbench.v		mem_system_perfbench.v
mem_system_randbench.v		mem_system_randbench.v
mem_system_ref.v		mem_system_ref.v
memc.syn.v		memc.syn.v
memc.v		memc.v
memory.v		memory.v
memory2c.syn.v		memory2c.syn.v
memory2c.v		memory2c.v
memory2c_align.syn.v		memory2c_align.syn.v
memory2c_align.v		memory2c_align.v
memv.syn.v		memv.syn.v
memv.v		memv.v
mux2_1.v		mux2_1.v
mux2_1_1bit.v		mux2_1_1bit.v
mux2to1.v		mux2to1.v
mux4_1.v		mux4_1.v
mux4_1_1bit.v		mux4_1_1bit.v
mux8_1.v		mux8_1.v
nand2.v		nand2.v
nand3.v		nand3.v
nor2.v		nor2.v
nor3.v		nor3.v
not1.v		not1.v